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Organization: Kai
An incomplete SoC
Software Type: Soft IP
Organization: Digital Core Design
DCD’s RV32IMZicsr RISC-V Core The DRV32IMZicsr is a 32-bit RISC-V CPU with M, Zicsr extensions, and External Debug support. The Core belongs to the latest DCD’s DRVX Core Family, with: a five-stage pipeline, Harvard architecture flexible size of program and data memory together with their allocation in address space. It is possible to select CPU interface as: AXI, AHB, Native. The DRV32IMZicsr was developed as ISO26262 Safety Element out of Context (SEooC) and is technology independent, and compatible with all FPGA and ASIC vendors. The DRV32IMZicsr can be used along with a wide range of DCD’s peripherals, like e.g. DMA, SPI, UART, PWM, CAN etc. This holistic approach makes the DRV32IMZicsr core a good choice for application for e.g. Automotive, Internet of Things, Embedded, Consumer Electronics, and more. The DRV32IMZicsr is a 32-bit core with 32 General Purpose Registers. It performs arithmetic and logic instructions, loads, stores, conditional branches, and unconditional jumps. The proper usage of base instructions provides an additional set of pseudo instructions which are available in the RISC-V assembly language. The M extension enables the use of additional integer multiplication and division instructions due to Multiplication and Division unit, which is responsible for handling these instructions. The Zicsr extension provides the means to access Control and Status Registers, which in turn enables interrupt and exception handling according to version 20211203 of The RISC-V Instruction Set Manual Volume II: Privileged Architecture. With Zicsr extension DRV32IMZicsr core is also equipped with performance counters and timers. External Debug support utilizes JTAG debug interface and is implemented with conformance to the RISC-V Debug Specification 0.13.2 and 1.0.0. That allows core debugging with all the tools compatible with this specification available on the market. The DRV32IMZicsr core is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of the SoC design flow. DESIGN FEATURES: ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G. Altera / Intel, Xilinx / AMD, Lattice, Microsemi / Microchip, and others. TSMC UMC SK Hynix and others.
Software Type: Soft IP
Organization: Digital Core Design
The DRV64IMZicsr is a 64-bit RISC-V CPU with M, Zicsr extensions and External Debug support. As a part of the DRVX Core Family this unique CPU offers: five-stage pipeline, Harvard architecture, flexible size of program and data memory together with their allocation in address space. To give you freedom of choice, you can easily select the CPU interface: AXI, AHB Native. The DRV64IMZicsr was developed as ISO26262 Safety Element out of Context (SEooC) and is technology independent, and compatible with all FPGA and ASIC vendors. As we believe in DCD that one CPU is not enough… you can easily use it with a wide range of DCD’s peripherals, including DMA, SPI, UART, PWM, CAN, and more. These unique features make DRV64IMZicsr core a good choice for many applications like e.g. Automotive, Internet of Things, Embedded, Consumer Electronics and many more. The DRV64IMZicsr is 64-bit core with 32 General Purpose Registers. It performs arithmetic and logic instructions, loads, stores, conditional branches, and unconditional jumps. What’s more, proper usage of base instructions provides an additional set of pseudo instructions which are available in the RISC-V assembly language. The M extension enables the usage of additional integer multiplication and division instructions due to Multiplication and Division unit which is responsible for handling these instructions. The Zicsr extension provides the means to access Control and Status Registers which in turn enables interrupt and exception handling according to version 20211203 of The RISC-V Instruction Set Manual Volume II: Privileged Architecture. With Zicsr extension DRV64IMZicsr core is also equipped with performance counters and timers. External Debug support utilizes JTAG debug interface and is implemented with conformance to the RISC-V Debug Specification 0.13.2 and 1.0.0. That allows core debugging with all tools compatible with this specification available on the market. The DRV64IMZicsr core is delivered with fully automated test bench and a complete set of tests, allowing easy package validation at each stage of the SoC design flow.
License Type: Copyleft
Software Type: Soft IP
Software Type:
Organization: Indian Institute of Science, Bangalore
32-bit, 5-Stage Pipelined RISC-V Core
License Type: Proprietary
Software Type: Soft IP
Organization: Indian Institue of Science, Bangalore
32-bit, 5 Stage Pipelined RISC-V Core with Vector Extension Support
License Type: Proprietary
Software Type: Soft IP
Organization: StarFive
JH7110 is a high-performance RISC-V SoC featuring high-performance, low-power-consumption and high-security. JH7110 is equipped with a 64-bit high-performance quad-core RISC-V processor core sharing 2 MB of cache coherency, whose working frequency is up to 1.5GHz. JH7110 has a rich high-speed native interface, supports the Linux operating system, and has powerful image and video processing system. The StarFive ISP is compatible with mainstream camera sensors, built-in image/ video processing subsystem supports H264/H265/JPEG codec, and 4K@30fps display. The integrated GPU makes its image processing capabilities stronger, such as 3D rendering. With high-performance, OpenCL/OpenGL ES/Vulkan support, JH7110 can further enhance intelligence and efficiency. JH7110 can complete a variety of complex image/video processing and intelligent visual calculations. Also, it meets multiple visual real-time processing requirements at the edge.
License Type: Mixed
Software Type: Chips
Organization: Federal University of Semiarid Region - UFERSA
A small 32-bit RISC-V processor suitable for resource constrained applications such as Internet of Things (IoT) designed using VHDL and tested in both FPGA and opensource ASIC flow.
License Type: Copyleft
Software Type: Soft IP
Organization: MINRES Technologies GmbH
TGC-A is a single issue core with a 3-stage in-order pipeline implementing RV32E Zicsr Zifencei.The core can be easily extended with custom instructions and supports a variety of on-chip bus interfaces.TGC-A is low power and low area core, suitable for embedded systems and ISO 26262 certifiable.
License Type: Proprietary
Software Type: Soft IP
Organization: MINRES Technologies GmbH
TGC-B is a single issue core with a 3-stage in-order pipeline implementing RV32I Zicsr Zifencei. The core can be easily extended with custom instructions and supports a variety of on-chip bus interfaces. TGC-B is RTOS capable, suitable for embedded systems and ISO 26262 certifiable.
License Type: Proprietary
Software Type: Soft IP
Organization: MINRES Technologies GmbH
TGC-C is a single issue core with 4-stage in-order pipeline implementing RV32IMC Zicsr Zifencei. The core can be easily extended with custom instructions using CoreDSL and supports a variety of on-chip bus interfaces. TGC-C is RTOS capable, suitable for IoT and edge applications and ISO 26262 certifiable.
License Type: Proprietary
Software Type: Soft IP
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