Skip to main content

RISC-V Exchange

The RISC-V Exchange hosts the hardware, software, services, and learning offerings in the RISC-V community. Browse the list or search for an offering below.

Arabic course in Computer Architecture taught in RISC-V ISA

Organization: Umm Al-Qura University

An Arabic course in Computer Architecture taught in RISC-V ISA based on Computer Organization and Design the Hardware/Software Interface, RISC-V Edition, David Patterson and John Hennessy by Dr. Ghassan F. Bati. http://www.uqu.edu.sa/gfbati

License Type: Copyleft

Learn Language: Arabic

Learning

Brief Tutorials of GD32V RISC-V MCU and TencentOS Tiny

Organization: BMRTech

This tutorial introduces basic background knowledge of IoT, IoT OS and RISC-V. Then it elaborates on the function of IoT OS kernel function and communication components. Application instances of GD32VF103 MCU and TencentOS tiny are presented.

License Type: Open custom

Learn Language: Chinese (Simplified)

Learning

Building Applications with RISC-V and FreeRTOS (LFD112x)

This course is designed to provide the skills you need to build embedded systems with RTOS capabilities for real-time applications. Real time operating systems (RTOS) play an important role in any embedded system, enabling users to control the time critical functions required to be handled within specific timeframes for the effective use of those systems. FreeRTOS is an open source RTOS that has been used in various embedded systems and has been effectively ported onto various processors.

Learn Language: English

Learning

Computer Architectures Course (BE5B35APO)

Organization: Czech Technical University in Prague

Classical Computer Architectures course using RISC-V as model architecture starting with number representation, building single cycle CPU, adding cache, pipeline, hazard unit,input output etc.. with demonstration on QtRvSim simulator with online version available.

License Type: Mixed

Learn Language: English

Learning

Embedded development and applications on RISC-V processor

Organization: BMRTech

It's a series of video training courses to give a brief introduction for embedded applications development on RISC-V platforms.

License Type: Open custom

Learn Language: Chinese (Simplified)

Learning

Embedded development for RISC-V processor I

Organization: BMRTech

This course video is a paid course which covers the introduction of RISC-V processor ISA and interrupt mechanism, GD32VF103 chips and peripherals, development tools and software libraries. In terms of application, take FreeRTOS as an example to introduce the porting and booting of a FreeRTOS on RISC-V, and explain the basic use of FreeRTOS through examples, including task creation, interruption of interaction with tasks and communication between tasks. And through the visual RTOS analysis tool - Tracealyzer, you can intuitively view the behavior of RTOS in a multitasking environment.

License Type: Open custom

Learn Language: Chinese (Simplified)

Learning

Embedded development for RISC-V processor II (Excerpt versionz)

Organization: BMRTech

This course video is excerpted from the Embedded development for RISC-V processor II. It's a paid course that covers RISC-V embedded eco-system, RISC-V ISA and assemble language, RISC-V software optimization, etc.. Project create, build, debug configurations and assemble language programming are showed under Segger Embedded Studio and Nuclei Studio. MCU functions, peripherals and interrupt handling are described based on GD32VF103. Then porting and booting of a FreeRTOS multi-task application is presented. The multi-task behavior of the application is visualized by using the RTOS analysis tools, including Tracealyzer and SystemView.

License Type: Open custom

Learn Language: Chinese (Simplified)

Learning

Embedded development on RISC-V processor II

Organization: BMRTech

This course video is a paid course which covers the analysis of the current developer ecological status of RISC-V, RISC-V processor architecture, basic kernel introduction, assembly language use, and program optimization technology. In this course, you will learn how to create a project based on Segger Embedded Studio environment, understand RISC-V MCU functions , peripherals and interrupt handling implementation based on GD32VF103 MCU. Then introduce the FreeRTOS multitasking application, the migration and startup process on RISC-V, and intuitively view the behavior of RTOS in the multitasking environment through the visual RTOS analysis tools -Tracealyzer and SystemView.

License Type: Open custom

Learn Language: Chinese (Simplified)

Learning

LFD117x Foundations of RISC-V Assembly Programming

Organization: LinuxFoundationX

A basic understanding of the assembly language with RISC-V is vital for hardware-related programming. Tasks like debugging and identifying performance-critical program sections are easier to achieve with the foundations of Assembly. This course is designed for software developers who want to understand what instructions a RISC-V microprocessor finally executes for any software running on it. While this is an introductory course, developers should have a basic understanding of programming concepts and methodologies in order to benefit from the course material.

License Type: Permissive

Learn Language: English

Learning

Microcontroller Applications with RISC-V (LFD115x)

Create simple embedded applications with a RISC-V microcontroller using a user-friendly integrated development environment (IDE). This course provides some basic experience in designing and developing deeply embedded bare metal applications using a microcontroller with a RISC-V core. The course is the first step to creating embedded systems using a host of new microcontrollers that use an open instruction set architecture (ISA) as an alternative to a proprietary option.

Learn Language: English

Learning

Updates and edits to existing entries, as well as contribution of new entries, are welcome! Please submit your inputs here.

Stay Connected With RISC-V

We send occasional news about RISC-V technical progress, news, and events.