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Cache Subsystem Design Engineer

Cache Subsystem Design Engineer

Website SiFive

We bring RISC-V, software, and silicon experts together to innovate with a modern, software-driven approach to semiconductors.

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms have enabled leading technology companies around the world to innovate, optimize, and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, datacenter, mobile, and consumer. With SiFive, the future of RISC-V has no limits. For more information, please visit www.sifive.com.

As a Cache Subsystem Microarchitect/RTL design engineer at SiFive, you will be part of a team of engineers who are passionate about designing industry-leading CPU cores and cache subsystems, based on the revolutionary open-source RISC-V architecture. We are looking for people who are as excited as we are about working in a fast-paced dynamic environment to bring new hardware IP to market quickly, with high quality and exceptional performance.

Responsibilities:

  • Architect, design and implement new cache subsystems in SiFive’s RISC-V CPU core generators and enhance features and performance in existing ones.
  • Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.
  • Perform initial sandbox verification, and work with design verification team to create and execute detailed verification plans.
  • Work with physical implementation team to implement and optimize physical design to meet frequency, area, power goals.
  • Collaborate with performance modeling team for performance exploration and optimization to meet performance goals.

Requirements:

  • 5+ yrs of recent industry experience in high-performance, energy-efficient CPU cache subsystem designs.
  • Expertise in multi-level coherent CPU cache architectures and designs.
  • Knowledge of RISC-V architecture and TileLink is a plus.
  • Experience with Scala and/or Chisel is a plus.
  • Attention to detail and a focus on high-quality design.
  • Ability to work well with others and a belief that engineering is a team sport.
  • Knowledge of at least one object-oriented and/or functional programming language.
  • BS/MS degree in EE, CE, CS or a related technical discipline, or equivalent experience.

To apply for this job please visit boards.greenhouse.io.

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