CPU Design Engineer | RISC-V | EDA
Cutting-edge processor IP based on the RISC-V open ISA
TL;DR 🙂 Application processors, Embedded processors – CodAL – RISC-V ISA – Processor Microarchitecture – Linux-capable cores – CPU – Multi-core CPU architectures – International team – Start-up culture – Agile
Locations: Brno, Prague, Remote CZ, France (Villeneuve-Loubet), Germany (Munich), Spain/Barcelona (Remote)
Department: Application/Embedded Teams
Employment Type: Full-Time
Experience: Mid-Senior Level
We at Codasip are happy to announce we are growing our HW Design teams with professional enthusiasts. You want to join a team where each clock cycle matters, where each signal toggles for good reasons, where there are always ideas to do better, faster, safer, and be welcome. We are expanding our Portfolio of processor soft IPs and accelerators IPs to address the increasing demand of performance at low power in the RISC-V ecosystem.
What is unique at Codasip is our approach to design to speed up the development and leverage HW & SW co-design: we use our increasingly adopted architecture description language CodAL.
Together with our well-organised and highly collaborative international teams, located in the Czech Republic, Germany, France and UK you will be responsible for the development of the core or of the accelerator microarchitecture;
- Engineering degree or equivalent
- Good knowledge of modern CPU architectures (ideally RISC-V) and micro-architectures, or alternatively track of records in the design of complex pipelined designs.
- Advanced knowledge of at least one Hardware Description Language (preferably – Verilog/SystemVerilog)
- Sharp understanding of physical implications when designing at a higher level of abstraction (digital design synthesis and implementation flow).
- Skills to design and optimise a module around a given PPA point.
- Practical expertise in versioning tools (preferably git)
- Proficiency in scripting languages (Shell, Python, Tcl)
- Practical usage of Linux
- Proficiency in digital design synthesis and implementation flow
- Communicative English. Our team is highly distributed, so English is the main language
- Hands-on experience with HW simulators and synthesis tools
- Proficiency in computer architecture and systems
- Ability to write clear and concise code
- Active interest in the field and self-education
- Analytical thinking, self-sufficiency, team spirit, open-minded and passion to learn
OUR TECHNOLOGICAL BASIS:
- CodAL (Company Architectural Language)
- QuestaSim, Verilator
- Cadence Genus
- Jira, Confluence
OUR PLUS POINTS:
- Focus on the real development of real processors
- Working on innovative IoT processors and unique processors, configurations, optimizations and customisations technology
- Opportunity to work with experienced HW and SW engineers
- Receptivity to your own innovations and ideas
- Flexible working hours
This Position is relevant for any of our design centres in Europe.
WHO IS CODASIP:
Codasip was founded on a simple belief – we could bring together the brilliance of microprocessor architects and software engineers and capture it in tools that make design simpler, faster, and less expensive. The company was created in 2014 with the mission of democratizing processor design by utilizing our own CodAL architecture description language.
Nowadays Codasip is a leading supplier of processing solutions for IC designers, offering products based on open standards such as the RISC-V ISA, LLVM and UVM. We are a founding member of RISC-V International (formerly RISC-V Foundation) and we were the first company to offer a commercial RISC-V IP core in 2015. With more than 100 employees and offices in Europe, US and China, we are constantly open for talents who want to work on cutting-edge processor technologies, believe in the great potential of RISC-V.
We’re passionate about RISC-V processors. If you are, too – do not hesitate to apply 🙂
To apply for this job please visit codasip.bamboohr.com.