RISC-V Performance Modeling SIG is driving the development of Performance Modeling and Simulation Tools for use across RISCV membership to foster collaboration across the community. To that end, the SIG has developed a trace-driven performance model of an example RISC-V superscalar processor using C++ based on the Sparta simulation framework. The performance model, named Olympia, has been adopted by multiple organizations in both industry and academia.

We have identified set of features for further development of Olympia:
* Add support for execution-driven modeling
– https://github.com/riscv-software-src/riscv-perf-model/issues/14
* Model state of art branch predictors along with decoupled frontend using branch-prediction API, with an example being the BOOM processor frontend documented at https://docs.boom-core.org/en/latest/sections/branch-prediction/index.html
– https://github.com/riscv-software-src/riscv-perf-model/issues/143
– https://github.com/riscv-software-src/riscv-perf-model/issues/1
* Develop an API for Interconnect model and implement an example Interconnect microarchitecture.
– https://github.com/riscv-software-src/riscv-perf-model/issues/60
* Use the API for data/instruction prefetcher and implement an example prefetcher microarchitecture
– https://github.com/riscv-software-src/riscv-perf-model/issues/142
* Enhance the existing vector extension implementation
– https://github.com/riscv-software-src/riscv-perf-model/issues/15#issuecomment-2174028723
* Carry out performance studies using Olympia, such as
– Explore/compare the relationship between operations fused in the machine vs. custom instructions that the compiler is aware of.
– Measure and explain impact of varying sizes of various structures such as instruction/data caches, load/store queues

We invite mentees who are passionate about computer architecture and performance modeling to join us in this effort. This is an excellent opportunity to further develop a key piece of software that has high visibility across the entire RISCV community as well as to be able to work with veteran engineers from the industry involved in this project.

Repository URL: https://github.com/riscv-software-src/riscv-perf-model

Learning Objectives

* Collaborate with SIG members to define microarchitecture to be modeled.
* Develop an understanding of Sparta modeling framework and use it to write efficient performance models
* Respond and address multiple iterations of reviewer feedbacks
* Document the modeled microarchitecture as well the code used for modeling
* Present and discuss work during SIG meetings

Applications open July 15 on the LFX Platform, additional details on required skills and a coding challenge found in LFX.

Questions about the process? Read the program details and timeline here, still have a question, reach out on the RISC-V Slack, #risc-v-mentorship-questions