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Sr. Staff Design Engineer – Microarchitect

Sr. Staff Design Engineer – Microarchitect

Website MIPS Technologies

We’re taking RISC-V to new heights!

We are seeking an experienced Sr. Staff Design Engineer – Microarchitect. In this role you will be responsible for leading and owning RTL development of one or more modules of a high-performance CPU core. This position will be responsible for all aspects of the design including Performance, Power, and Area.

You will:
Drive the micro-architecture and design of a critical CPU block or multiple blocks of a CPU core
Explore high-performance strategies working with the CPU modeling team
Perform Microarchitecture development and specification- from early high-level architectural exploration, through microarchitectural research and arrive at detailed specifications
Configure Design Features Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals
Perform Functional verification support and assist in the design verification strategy
Assist with the verification of RTL design performance goals
Partner with a multi-functional engineering team to implement and validate physical design aspects of timing, area, reliability, testability, and power

Ideally, you’ll have:
Hands-on working knowledge of the pipeline stages of an in-order or out-of-order high-performance CPU core is required
Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas:

Instruction fetch and decode, branch prediction
Instruction scheduling and register renaming
Out-of-order execution
Integer and Floating-point execution
Load/Store execution, prefetching
Cache and memory subsystems

Knowledge of Verilog and/or VHDL
Experience with simulators and waveform debugging tools.
Knowledge of logic design principles along with timing and power implications MS degree in Electrical or Computer Engineering with 5+ years or BS degree with 7+ years of practical experience

A plus if you have:
Experience with designing RISC-V, ARM, and/or MIPS CPU
Experience with Hardware multi-threading, virtualization, and SIMD designs
Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
Understanding of low-power microarchitecture techniques
Experience using a scripting language such as Perl or Python

Here’s what you can expect from us:
At MIPS, you’ll be a member of a fast-growing team of technologists that are creating the industry’s highest performance RISC-V processors. Small teams that are part of a non-compartmentalized structure – you’ll be able to understand and have an impact on the bigger picture. A great deal of autonomy, with support from some of the industry’s most experienced CPU engineers. An unlimited growth path – with the right skills, you can decide where you want to expand and grow in your role at MIPS. The opportunity to learn a great deal about the blossoming RISC-V architecture in cutting edge applications with industry leading customers.

At MIPS we provide meaningful benefits programs and products to our associates and their families. MIPS offers a competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave!

More about us:
MIPS is well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original MIPS RISC architecture, MIPS processors have shipped into billions of consumer and enterprise products.

Today, MIPS is once again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products: the MIPS eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, MIPS can accelerate development and deployment of RISC-V based solutions.

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