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Cache and memory engineer

Cache and memory engineer


European supplier of RISC-V IP cores

Are you passionate about microprocessor architecture? We need you! As a Senior Cache and Memory Design Engineer, you play a crucial role in designing and developing memory subsystem solutions for our semiconductor portfolio. You will work within the Cache and Memory Design Team and work closely with other teams’ highly skilled engineers to create efficient and high-performance memory subsystems that are essential for modern designs.

What we offer? Flexible work schedules, competitive pay, a highly learning environment, and opportunities for advancement. Come and join us in the beautiful city of Barcelona!. Candies, coffee and free spanish lessons included!. (Visa sponsorship if required)

Master or PhD
English C1
Industrial experience +8 years
Knowledge of coherency
Experience defining address map, CHI and CXL protocols, cache and bank memories
Proficiency in RTL design using Verilog or VHDL
Knowledge of scripting languages (Python, Perl, Bash, TCL)
Experience with Timing and Timings Constraints
Knowledge of revision control methodology and tools ( git, svn)
Experience with basic block level testing

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