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We send occasional news about RISC-V technical progress, news, and events.
Dave is a UC Berkeley professor, a Google distinguished engineer, the RISC-V International Open Source Laboratory Director, and the RISC-V International Vice-Chair. His RISC, RAID, and Network of Workstation projects at Berkeley helped lead to major industries and seven books. The newest book is The RISC-V Reader, co-authored by Andrew Waterman, and the best known is Computer Architecture: A Quantitative Approach. He and his co-author John Hennessy shared the 2017 ACM A.M Turing Award. He received BA, MS, and PhD degrees from UCLA. Our filmmaker Grace Patterson is his granddaughter.
Grace is a senior at Mills College, pursuing a Bachelor of Arts in Art & Technology and a Bachelor of Arts in Communications. Since 2015 she has been directing, editing, and producing short films, which have featured in six film festivals. Grace has self produced more than ten films, with the “10 Year Anniversary of RISC-V” project being her biggest editing project yet. Check out some of her other work here.
Andreas is the founder at Zero ASIC, a startup on a mission to reduce the barrier to custom silicon. Andreas has spent the better part of his career optimizing processor energy efficiency and design implementation costs. From 2017 to 2020, Andreas served as a program manager at DARPA where he created and managed national research programs in design automation, open source hardware, machine learning, parallel compilers, heterogeneous integration, and analog computing. Andreas received his BA in Physics (’96), BS in EE (’96), and MS in EE in (’97) from the University of Pennsylvania.
Andrew serves as SiFive’s Chief Engineer and co-founder. Andrew received his PhD in Computer Science from UC Berkeley, where, weary of the vagaries of existing instruction set architectures, he co-designed the RISC‑V ISA and the first RISC‑V microprocessors with Yunsup Lee. Andrew is one of the main contributors to the open-source RISC‑V based Rocket chip generator and the Chisel project. Andrew also has an MS from UC Berkeley and a BSE from Duke University.
Andrew is the William Eckhardt Professor at the University of Chicago and Editor-in-Chief of the Communications of the ACM. Chien is a global research leader in parallel computing, computer architecture, clusters, and cloud computing. Dr. Chien served as Vice President of Research at Intel Corporation from 2005-2010, leading long-range and “disruptive technologies” research. While at Intel, working with Microsoft and NSF, Chien was instrumental in creation of the Universal Parallel Computing Research Centers (UPCRC) at Berkeley where RISC-V was born. Dr. Chien is an ACM, IEEE, and AAAS Fellow, and has a PhD, MS, and BS from M.I.T.
Arvind is Johnson Professor of Computer Science and Head of CS Faculty at MIT. His current research focus is on the rapid development of embedded systems. Arvind received his PhD from the University of Minnesota (1973) and his BTech from IIT Kanpur (1969) and founded Sandburst (1999) and Bluespec (2003). Arvind is an ACM Fellow, an IEEE Fellow, a member of the National Academy of Engineering and the American Academy of Arts and Sciences.
Takoma Park MD
Calista is the CEO of RISC-V International. Prior to RISC-V International, Calista held a variety of roles at IBM, including Vice President of IBM Z Ecosystem where she led strategic relationships and broader engagement across the industry. Prior to IBM, she was an entrepreneur in four successful start-ups in the IT industry. Calista holds degrees from the University of Michigan and Northwestern University.
David is the lead of Fedora/RISCV efforts and Linux Distribution Software Engineer at SiFive. Prior to focusing on RISC-V, David used to work at CERN as Release Manager for CMS Software and later worked on R&D in computing with main focus on alternative architectures (ARMv8 64-bit and PowerPC)
Frankwell is the President and co-founder of Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores. Under his management, Andes Technology has been recognized as one of the leading suppliers of embedded CPU IP in the semiconductor industry. Through the end of 2019, cumulative shipments of Andes-embedded SoCs has reached 5 billion. Frankwell received BSEE degree of Electrophysics from the National Chiao-Tung University, Taiwan, and MSEE degree of Electrical and Computer Engineering from Portland State University, Oregon, USA.
Los Altos Hills, California
Frans is a VP of hardware engineering managing NVIDIA’s multi-media hardware department. He is responsible for RISC-V, security, and cryptography accelerators, a deep learning accelerator, and camera, video, and display processing hardware. Frans also serves on the board of two open source organizations: the RISC-V foundation and AOM. He is as passionate about technology now as he was when he graduated from the Eindhoven University of Technology in 1985 with a MSc in Computer Science.
Madhu is the CEO and co-founder of InCore Semiconductors, India’s first processor IP company. He is also a coordinator of the IIT Madras Shakti project and a collaborator with the Robert Bosch Centre for Data Sciences and AI. He is a veteran of the electronics and computing technology industry with more than 3 decades of experience in running tech startups and R&D organizations across the world.
San Francisco, CA
Helena is a Security Technologies Fellow at Rambus (Cryptography Research). She directs the foundational security technologies team in charge of research in crypto and post-quantum crypto, side-channel attack countermeasures, secure memories, and Security IP creation overall. She was formerly CTO at Intrinsic-ID and led the Security team at Gemplus before that. She holds a PhD in cryptography and has authored more than 50 peer-reviewed papers and has over 20 issued patents.
Krste is SiFive’s Chief Architect and a Co-Founder. He is also a Professor in the EECS Department at UC Berkeley, where he also serves as Director of the ADEPT Lab. Krste leads the RISC‑V ISA project at Berkeley, and is Chairman of RISC‑V International. Krste received his PhD from UC Berkeley, and a BA in Electrical and Information Sciences from the University of Cambridge. He is a Fellow of the ACM and a Fellow of the IEEE.
Luca holds the chair of digital Circuits and systems at ETHZ and is Full Professor at the Universita di Bologna. He has been a visiting professor at Stanford University, IMEC, and EPFL. He served as chief architect in STmicroelectronics France. His research interests are in energy-efficient parallel computing systems, smart sensing micro-systems, and machine learning hardware. He received a PhD from Stanford University. He is a Fellow of the ACM, a Fellow of the IEEE, and a member of the Academia Europaea.
Martin is the former EVP and CTO at Western Digital and is now an advisor to the CEO. Fink joined Western Digital in January 2017. Previously, he served as CTO, EVP and Director of Hewlett Packard Labs at HPE Inc and as CTO and EVP of HP, Inc, overseeing HP Labs. In his 30-year career at HP Inc and HPE Inc. Fink worked in a wide range of roles. Fink led the open source and Linux strategy efforts across the company, helping to gain external market leadership. Fink is listed as co-inventor on multiple patents and is the author of The Business and Economics of Linux and Open Source.
Mike is the President and founder of Rumble Development Corporation. Rumble is a small electronic design firm, specializing in the development of low power and high performance cameras. Rumble also licenses image processing and compression IP to many customers. Michael received his undergraduate degree from Harvard University, a Masters degree in Mathematics from the University of Cambridge, and a Ph.D. in Physics from Harvard University.
London, United Kingdom
Richard studied Mathematics and Computer Science at Imperial College, London, at the same time working on the hardware design and testing of X-ray detectors at Daresbury Laboratory in Cheshire, UK. He went on to co-found three start-up companies in the fields of networking, educational software, and search engine optimization. He then joined Red Hat where today he works on virtualization, storage, RISC-V, unikernels, and researching other new technologies.
Rick is President & CEO of the OpenHW Group a not-for-profit, global organization where developers collaborate on open source cores, related IP, tools, and software projects such as the CORE-V Family of open source RISC-V cores. Previously, Rick was Executive Director of the RISC-V Foundation (now RISC-V International) which he founded in 2015 with the support of over 40 Founding Companies driving a new frontier of processor innovation. Rick holds an Executive MBA degree from the University of Ottawa and is an honors graduate of the faculty of Electronics Engineering Technology at Algonquin College.
Nikhil is a co-founder and CTO of Bluespec, Inc.. He received his Ph.D in Computer Science from University of Pennsylvania, was an Associate Professor at MIT, and a researcher at Digital Equipment Corp., working in Programming Languages, Computer Architecture, and Parallel Computing. He’s worked on RISC-V CPU and system designs since 2013, and chaired the RISC-V ISA Formal Specification group 2017-2019. He is a member of ACM, IEEE, and IFIP WG2.8 on Functional Programming.
Palo Alto, CA
Stefan is Managing Director at Sutter Hill Ventures (SHV), lead investor in SiFive and also served as the company’s founding CEO. At SHV, Stefan leads investments in computing, networking and security and sits on several boards. Prior to joining SHV in 2012, Stefan served as EVP/GM of The Platform Systems Group at Juniper Networks, overseeing most of its R&D. After joining Juniper’s founding engineering team as an ASIC designer in 1997, his operating career includes several leadership roles at Juniper and Cisco. Stefan holds a BS in Electrical Engineering and Computer Science from Duke University, and a MS in Electrical Engineering from Stanford University.
El Sobrante, CA
Tami is a Program Administrator at UC Berkeley with over 20 years experience in the field. She is currently the administrative team lead for the ADEPT Project at Berkeley. Prior to that she was the admin team lead of the ASPIRE and Par Lab projects, and was interim secretary and treasurer of the RISC-V Foundation.
San Jose, CA
Ted is head of product architecture and planning for Microchip’s FPGA BU, where he is responsible for defining its roadmap for low power, secure, reliable FPGAs and SoC FPGAs. He joined Actel (now part of Microchip) in 1987 and held roles in process engineering and product engineering before assuming his current role in 2003. He is a Technical Fellow and co-inventor on 35 U.S. patents. Prior to joining Actel, he worked at LSI Logic. Ted has served on the board of RISC-V International since its inception in 2016. He has a Bachelor of Science in chemical engineering from Cornell.
Redwood City, CA
Yunsup is SiFive’s Chief Technology Officer and a co-founder. Yunsup received his PhD from UC Berkeley, where he co-designed the RISC‑V ISA and the first RISC-V microprocessors with Andrew Waterman, and led the development of the Hwacha decoupled vector-fetch extension. Yunsup also holds an MS in Computer Science from UC Berkeley and a BS in Computer Science (CS) and Electrical Engineering (EE) from the Korea Advanced Institute of Science and Technology (KAIST).
Zhangxi is a co-director of the RISC-V international open-source laboratory (RIOS) at Tsinghua-Berkeley Shenzhen Institute (TBSI), where he is an adjunct professor. Zhangxi is the founder and president of RiVAI Technologies Co. LTD working on energy-efficient RISC-V processors. He is on the Board of Directors of RISC-V International. Zhangxi received his MS and PhD in Computer Science from Berkeley in the Parallel Computing Lab, and a BE in Electronics Engineering from Tsinghua University.
San Jose, California
Zvonimir is the Research Staff Member and Senior Director of Next Generation Platform Technologies Department in a Western Digital Corporation. Zvonimir is Chairman of CHIPS Alliance, Chair of OpenCAPI org, and on the Board of Directors of RISC-V International. He received his BS in EE (1994) from the University of Belgrade and his MS (1995) and PhD (1999) in applied physics from Caltech.
We send occasional news about RISC-V technical progress, news, and events.