RISC processor designs, labelled as such, date back to the early 1980s and have always been of academic interest. Academics created the original RISC instruction set DLX for use in the first edition of the Hennessy & Patterson textbook Computer Architecture: A Quantitative Approach in 1990. However, this ISA was intended primarily for educational use. The RISC-V ISA is the fifth generation of this original work and is quite suitable in both commercial and academic environments.
RISC-V Genealogy Report and Collapsible Tree
RISC-V consists of a base set of instructions called RV32I along with optional extensions for multiply and divide (RV32M), atomic operations (RV32A), single-precision floating point (RV32F), and double-precision floating point (RV32D). The base and these four extensions are collectively called RV32G. The report below, from Tony Chen and Dave Patterson of UC Berkeley, discusses the historical precedents of RV32G. The report examines 18 prior instruction set architectures, chosen primarily from major proprietary RISC instruction sets and earlier UC Berkeley RISC architectures.
The collapsible tree below shows the lineage and genealogy each instruction found in the RISC-V ISA by tracing each instruction’s origin back to DLX and RISC-I through RISC-IV iterations. By clicking on each of the node icons in the tree below, you can navigate through the lineage of each RISC-V instruction.