RISC-V International News

The Importance of a Standardized Processor Trace

By Gadge Panesar, Chief Technology Officer of UltraSoC and Chair of the RISC-V Processor Trace Task GroupFor the last eighteen months, the RISC-V International Association Processor Trace Task Group has gone to great lengths to prioritize getting the RISC-V Processor Trace Specification polished and ready for the wider world. I’m proud to have chaired the Group, and to have witnessed the hard work we put in to get it done….

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RISC-V: An Open Approach to System Security

By Helena Handschuh, Security Technologies Fellow at Rambus Inc. and Chair of the RISC-V Foundation Security Standing CommitteeLeveraging open source technology delivers great benefits for software and hardware development, but also for security.In one of this year’s RSA Conference keynotes, it was described how managing open source software is getting more and more complicated because of the difficulty of backtracking to origins when a software bug or a security bug…

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Inaugural class of RISC-V Ambassadors

Congratulations to our inaugural class of RISC-V Ambassadors! Please join me in recognizing the amazing contributions that our first RISC-V Ambassadors have already made to the RISC-V community. These individuals have uncommon energy, strong technical insight, unwavering dedication, and lead through collaboration. Their creativity and efforts to grow RISC-V adoption, seed innovation across industries, and lead within many geographies has helped us build a broad and deep community of RISC-V…

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RISC-V Foundation Announces Ratification of the Processor Trace Specification

Ratification signifies another breakthrough for the thriving RISC-V ecosystemSan Francisco – March 9 2020 – The RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), today announced the ratification of the processor trace specification. The new standard trace encoder algorithm allows engineers and developers to see exactly what instructions a core is executing, step…

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RISC-V is not an “open-source processor” | Krste Asanovic, Chairman of the Board, RISC-V

Free and open standards are common in the computing industry, with instruction sets being an odd exception where the industry has tolerated proprietary interfaces, until now.  With the excitement around the arrival of the free and open RISC-V instruction set architecture (ISA), many are a little confused about the difference between a specification and an implementation.  There is no such thing as “the RISC-V core” — there are dozens of…

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RISC-V Foundation Showcases Unprecedented Momentum and Growth at Embedded World 2020 

The RISC-V Foundation booth will include live demonstrations and talks of RISC-V implementations from fourteen membersWHERE: Hall 3A, Booth No. 3A-536, NürnbergMesse, Messezentrum 1, 90471 Nürnberg, GermanyWHEN: Tuesday, Feb. 25 – Thursday, Feb. 27, 2020WHAT: At Embedded World 2020, the RISC-V Foundation will be exhibiting at Hall 3A, Booth No. 3A-536, and will feature live demonstrations from co-exhibiting RISC-V Foundation members Andes Technology, CHIPS Alliance, CloudBEAR, Codasip, Embecosm, GreenWaves Technologies, Imperas Software, Intrinsic…

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RISC-V Foundation & Members At Embedded World 2020

Join us at the Embedded World 2020 Exhibition & Conference from Tuesday, Feb. 25 to Thursday, Feb. 27, 2020 at the NürnbergMesse in Nuremberg, Germany. Visit Our Booth Featuring Fourteen RISC-V MembersThe RISC-V Foundation booth will feature fourteen pods from RISC-V members Andes Technology, CHIPS Alliance, CloudBEAR, Codasip, Embecosm, GreenWaves Technologies, Imperas Software, Intrinsic ID, OneSpin Solutions, OpenHWGroup, SiFive, Syntacore and UltraSoC. Visit us in Hall 3A, Booth No. 3A-536….

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