About the RISC-V ISA
RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The final user-level ISA specification, a draft privileged ISA specification, and a suite of RISC-V software tools including a GNU/GCC software tool chain, GNU/GDB debugger (upstream), an LLVM compiler, a Spike ISA simulator, QEMU (upstream), and a verification suite is available for download now.
You can also visit the UC Berkeley Architecture Research projects page to see a number of RISC-V based projects including a high-performance, energy-efficient Rocket processor (a 64-bit RISC-V single-issue in-order core), suitable for both high-speed simulation and full synthesis, is available for download.
Our intent is to provide a long-lived open ISA with significant infrastructure support, including documentation, compiler tool chains, operating system ports, reference software simulators, cycle-accurate FPGA emulators, high-performance FPGA computers, efficient ASIC implementations of various target platform designs, configurable processor generators, architecture test suites, and teaching materials.
Key Features of the RISC-V ISA:
- Delivers a new level of software and hardware freedom on architecture in an open extensible way.
- Open ISA delivers easier support from a broad range of operating systems, software vendors and tool developers.
- The open source of hardware, RISC-V does not rely on a single supplier – offers multiple suppliers, therefore, supports unlimited potential for future growth.
- No other ISA is architected like the RISC-V ISA, allowing for user extensibility of the architecture without breaking existing extensions or incurring software fragmentation