This content is reproduced for convenience from the GitHub Wiki page on this topic.

The original page is available at:

https://github.com/riscv/riscv-wiki/wiki/RISC-V-Software-Status

RISC-V Software Ecosystem Overview

This document captures the status of the RISC-V Software Ecosystem. Please add to the list and fix inaccuracies.

We would like to enlist community help for the software ports in the Help Wanted section.

Simulators

riscvOVPsim - A FREE, Complete, Fully Functional, Configurable RISC-V Simulator
  • Maintainer(s): Imperas Software, Ltd., using OVP Open Standard APIs (www.imperas.com)
  • Version: 01 Nov 2018 Version: 20181101.0
  • Upstream repository: https://github.com/riscv/riscv-ovpsim
  • Privileged Spec: Privilege 1.10, 1.11a (April 2018 draft)[not hypervisors as currently in flux]
  • User Spec: RISCV.org User 2.2, 2.3a (April 2018 draft)
  • Compliance status: passes all 12 RISC-V Foundation Compliance Test Suites (6-Dec-2018)
  • Model license: Apache 2.0
  • The riscvOVPsim simulator implements the full and complete functionality of the RISC-V Foundation's public User and Privilege specifications.
  • Developed to assist RISC-V adopters to become compliant to the RISC-V specifications. The latest RISC-V compliance test suite and framework can be downloaded from https://www.github.com/riscv/riscv-compliance.
  • riscvOVPsim includes an industrial quality model and simulator of RISC-V processors for use for compliance and test development. It has been developed for personal, academic, or commercial use, and the model is provided as open source under the Apache 2.0 license. The simulator is provided under the under Open Virtual Platforms (OVP) Fixed Platform Kits license that enables download and usage. riscvOVPsim and Imperas RISC-V support is actively maintained and enhanced.
  • Runtime configurable settings for all RISC-V specification options makes it very easy to compare run time results with any RTL implementations.
  • Full commercial features including variant selection, comprehensive trace, GDB/Eclipse graphical source code debug, semihosting, and RISC-V foundation signature dump facility for compliance testing.
  • The simulator is command line configurable to enable/disable all current optional and processor specific options.
  • The simulator is developed, licensed and maintained by Imperas Software and it is fully compliant to the OVP open standard APIs.
  • User Guide available: https://github.com/riscv/riscv-ovpsim/blob/master/doc/riscvOVPsim_User_Guide.pdf
  • Model source available: https://github.com/riscv/riscv-ovpsim/tree/master/source
DBT-RISE-RISCV
  • Maintainer(s): MINRES Technologies (www.minres.com)
  • Version: HEAD
  • Future work: cycle estimation, code coverage collection, full support of rv64 and base ISA extensions
  • Upstream repository: https://github.com/Minres/DBT-RISE-RISCV
  • Privileged Spec: 1.10
  • User Spec: 2.2
  • Licensing: BSD-3-Clause
FireSim
  • Maintainers: Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Berkeley Architecture Research
  • Status: Fully open source, actively maintained, support on mailing list
  • Website: https://fires.im
  • Upstream repository: https://github.com/firesim/firesim
  • Documentation: https://docs.fires.im
  • Privileged Spec: 1.10
  • User Spec: 2.2
  • Automated Cycle-exact FPGA-Accelerated Full-System Simulation of Rocket Chip-based systems on EC2 F1, derived from Rocket Chip RTL
  • Scalable, simulates one to thousands of nodes, with or without a cycle-accurate Ethernet network simulation
  • Includes peripherals like UART (SiFive), Block Device (ucb-bar), Ethernet NIC (ucb-bar)
  • Includes full target software stack, including RISC-V Linux version, buildroot, fedora images
  • ISCA 2018 Paper: https://sagark.org/assets/pubs/firesim-isca2018.pdf
  • Licensing: BSD
gem5
Imperas
  • Status: commercially supported solution
  • Website: http://www.imperas.com/riscv
  • Privileged Spec: Privilege 1.10, 1.11a (April 2018 draft)[not hypervisors as currently in flux]
  • User Spec: RISCV.org User 2.2, 2.3a (April 2018 draft)
  • Compliance status: passes all 12 RISC-V Foundation Compliance Test Suites (6-Dec-2018)
  • Processor ISA subsets available: RV32I, RV32IM, RV32IMC. RV32IMA, RV32IMAC, RV32IMAFD, RV32G, RV32GC, RV32GN, RV32E, RV32EC, RV64I, RV64IM, RV64IMC, RV64IMA, RV64IMAC, RV64G, RV64IMAFD, RV64GC, RV64GCN
  • Cores modeled: SiFive E31, E51, U54; Andes: N25, NX25, Microsemi MiV_RV32IMA
  • SoC, Modules, Platforms (under development): Microsemi: SmartFusion2, PolarFire, RTG4, IGLOO2, SiFive: U54-MC
  • Technology: JIT Code Morphing simulator running 1,000 MIPS speed with over 170 CPU models of all ISAs including 10+ RISC-V processor models
  • RISC-V ISS Product: very fast simulation of any RISC-V core with semihosting and GDB/Eclipse debug
  • RISC-V system emulator with library of over 200 components of Ethernet, USB, CAN, UARTs, and many other peripherals. Standard platforms available or develop your own virtual platforms
  • Multicore debugger available for SMP and AMP heterogeneous multi-core and many-core systems
  • Models boot standard OS such as FreeRTOS, Linux
  • High Speed: there a parallel simulation option called QuantumLeap to make use of the host PC parallelism to gain max simulation speed
  • Imperas also has over 100 models of all ARM (upto ARMv8): Cortex-A, Cortex-R and Cortex-M processors as well as many extendable platform kits of ARM reference designs that run many popular operating systems such as Linux, SMP Linaro Linux, FreeRTOS, ... http://www.ovpworld.org/variants
  • Imperas also has models of most other public ISAs and CPUs from various vendors including Andes, ARM, MIPS, Renesas, Power, Synopsys ARC, Xilinx MicroBlaze, Intel Altera Nios II, Microchip Microsemi, SiFive. http://www.ovpworld.org/groups
  • The Imperas simulators use the OVPworld models and there are over 200 behavioural models of peripheral components such as ethernet, usb, can, uart, dma, etc... http://www.ovpworld.org/peripherals and many example reference platforms http://www.ovpworld.org/platforms
  • Licensing: models available under Apache 2.0 open source license
jor1k
OVPsim
  • Status: freely available for non-commercial usage
  • Development: simulator, models and platforms actively being developed
  • Maintainer(s): Imperas Software (www.imperas.com)
  • Version: latest released listed on https://en.wikipedia.org/wiki/OVPsim
  • Website: http://www.ovpworld.org/riscv
  • Privileged Spec: Privilege 1.10, 1.11a (April 2018 draft)[not hypervisors as currently in flux]
  • User Spec: RISCV.org User 2.2, 2.3a (April 2018 draft)
  • Compliance status: passes all 12 RISC-V Foundation Compliance Test Suites (6-Dec-2018)
  • Processor ISA subsets available: RV32I, RV32IM, RV32IMC. RV32IMA, RV32IMAC, RV32IMAFD, RV32G, RV32GC, RV32GN, RV32E, RV32EC, RV64I, RV64IM, RV64IMC, RV64IMA, RV64IMAC, RV64G, RV64IMAFD, RV64GC, RV64GCN
  • Cores modeled: SiFive E31, E51, U54; Andes: N25, NX25, A25, AX25, Microsemi MiV_RV32IMA
  • SoC, Modules, Platforms (under development): Microsemi: SmartFusion2, PolarFire, RTG4, IGLOO2, SiFive: U54-MC
  • Models boot standard OS such as FreeRTOS, Linux
  • OVP also has over 100 models of all ARM (upto ARMv8): Cortex-A, Cortex-R and Cortex-M processors as well as many extendable platform kits of ARM reference designs that run many popular operating systems such as Linux, SMP Linaro Linux, FreeRTOS, ... http://www.ovpworld.org/variants
  • OVP also has models of most other public ISAs and CPUs from various vendors including Andes, ARM, MIPS, Renesas, Power, Synopsys ARC, Xilinx MicroBlaze, Intel Altera Nios II, Microchip Microsemi, SiFive. http://www.ovpworld.org/groups
  • The OVP simulators use the OVPworld models and there are over 200 behavioural models of peripheral components such as ethernet, usb, can, uart, dma, etc... http://www.ovpworld.org/peripherals and many example reference platforms http://www.ovpworld.org/platforms
  • Licensing: models available under Apache 2.0 open source license
QEMU
  • Maintainer(s): Sagar Karandikar (University of California, Berkeley), Bastian Koppelmann (University of Paderborn), Alex Suykov, Stefan O'Rear and Michael Clark (SiFive).
  • Version: 2.12.0
  • Upstreaming status: upstream
  • Future work:
  • Runtime changes to misa to model instruction set subsets.
  • SPI, GPIO support for SiFive E series.
  • Cadence Ethernet for SiFive U series.
  • RISC-V repository: https://github.com/riscv/riscv-qemu
  • Upstream repository: http://git.qemu.org/qemu.git
  • Privileged Spec: 1.9.1, 1.10
  • User Spec: 2.2
  • ABI:
Renode
  • Maintainer: Antmicro Ltd (http://antmicro.com)
  • Status: fully open source, with commercial support
  • Website: https://renode.io
  • Upstream repository: https://github.com/renode/renode
  • Privileged Spec: 1.10, 1.9.1
  • User Spec: 2.2
  • Support for full SoC emulation, runs unmodified software, fully deterministic execution
  • Integration with popular tools like GDB, Eclipse, Robot Framework, Wireshark etc
  • Support for multinode environments, with wired and wireless communication
  • Also supports ARM Cortex-A, ARM Cortex-M, X86 and PowerPC
  • Licensing: MIT
RISCVEMU
Spike
  • Maintainer(s): Andrew Waterman (SiFive), Yunsup Lee (SiFive)
  • Version: HEAD
  • Future work:
  • Upstream repository: https://github.com/riscv/riscv-isa-sim
  • Privileged Spec: 1.9.1
  • User Spec: 2.0
  • ABI:
Angel
  • Maintainer(s): Sagar Karandikar (University of California, Berkeley)
  • Status: No longer maintained.
  • Version:
  • Future work:
  • RISC-V repository: https://github.com/riscv/riscv-angel
  • Privileged Spec:
  • User Spec: 2.0
  • ABI:

Object toolchain

Binutils
LLVM
Cranelift

Debugging

Gdb
OpenOCD
GNU MCU Eclipse OpenOCD

A binary distribution of OpenOCD with support for RISC-V.

Imperas Multi Processor Debugger

C compilers and libraries

GCC
GNU MCU Eclipse RISC-V Embedded GCC (riscv-none-embed-gcc)

A binary distribution of the RISC-V toolchain, intended for bare-metal embedded applications.

clang
CompCert
Glibc
Newlib
  • Maintainer(s): Kito Cheng (Andes)
  • Version: 2.5.0
  • Status: Upstream, RISC-V support available starting in 2.5.0
  • Future work: Prepare patches for review.
  • RISC-V repository: https://github.com/riscv/riscv-newlib
  • Upstream repository: git://sourceware.org/git/newlib-cygwin.git
  • Privileged Spec:
  • User Spec: 2.0
  • ABI:
Musl
  • Maintainer(s):
  • Version:
  • Status:
  • Upstreaming status:
  • Future work:
  • RISC-V repository:
  • Upstream repository:
  • Privileged Spec:
  • User Spec: 2.0
  • ABI:

Boot loaders and monitors

coreboot
  • Maintainer(s): Ron Minnich (Google), Jonathan Neuschäfer
  • Version: master
  • Status: runs on spike, lowRISC/Nexys4DDR. Linux doesn't quite work yet.
  • Upstreaming status: upstream
  • Future work:
  • RISC-V repository:
  • Upstream repository: https://review.coreboot.org/cgit/coreboot.git/
  • Privileged Spec: 1.9
  • User Spec: 2.0
  • ABI:

More information:

UEFI
  • Maintainer(s): Abner Chang, Dong Wei (HP Enterprise)
  • Version:
  • Status:
  • Upstreaming status:
  • Future work:
  • RISC-V repository:
  • Upstream repository:
  • Privileged Spec:
  • User Spec: 2.0
  • ABI:

https://content.riscv.org/wp-content/uploads/2016/01/Tues1415-RISC-V-and-UEFI.pdf

Proxy Kernel/BBL

Kernels

Linux Kernel
seL4
RTEMS
FreeRTOS
  • Maintainer(s):
  • Version:
  • Status:
  • Upstreaming status:
  • Future work:
  • RISC-V repository:
  • Upstream repository:
  • Privileged Spec:
  • User Spec: 2.0
  • ABI:
Apache Mynewt
Zephyr

Operating systems

Fedora
  • Maintainer(s): Richard WM Jones, Stefan O’Rear, David Abdurachmanov
  • Version: 25
  • Status: Packages from @Core group (except dracut and plymouth) built against an old ABI; on hold until the bootstrap can be repeated and automated
  • Upstreaming status: Some changes upstreamed
  • Future work: Redo bootstrap with gcc-7, upstream all patches
  • RISC-V repository:
  • Upstream repository:
  • Privileged Spec: (depends on kernel used)
  • User Spec: 2.0
  • ABI: ~ September 2016 (not gcc-7)
  • Links: http://fedoraproject.org/wiki/Architectures/RISC-V
Debian
openSUSE
Yocto Project/OpenEmbedded
Poky
Gentoo
Parabola GNU/Linux-libre
OpenWrt
Busybox
Buildroot
  • Maintainer(s): Mark Corbin (Embecosm)
  • Version: master branch as of Sept 25, 2018
  • Status: Basic RISC-V 64-bit support for QEMU virtual target
  • Upstreaming status: upstream
  • Future work: -
  • Upstream repository: https://git.busybox.net/buildroot/
  • Privileged Spec:
  • User Spec:
  • ABI:
FreeBSD

https://content.riscv.org/wp-content/uploads/2016/01/Tues1445-freebsd-riscv-1.pdf

NetBSD

Compilers and runtimes for other languages

Go
OCaml
Jikes RVM (Java Virtual Machine)
  • Maintainer(s): Martin Maas (University of California, Berkeley)
  • Version:
  • Status:
  • Upstreaming status:
  • Future work:
  • RISC-V repository: Not yet public
  • Upstream repository: https://github.com/JikesRVM/JikesRVM
  • Privileged Spec:
  • User Spec: 2.0
  • ABI:
OpenJDK/HotSpot (Java Virtual Machine)
  • Maintainer(s): Alexey Baturo, Michael Knyszek, Martin Maas
  • contact seanhalle at intensivate dot com to join the porting effort
  • Version:
  • Status: Interpreter near completion (Oct 1, 2018)
  • Upstreaming status:
  • Future work: Modify MIPS backend code generator to emit RISC-V instructions
  • RISC-V repository: contact Sean Halle at Intensivate to be added
  • Upstream repository:
  • Privileged Spec:
  • User Spec: 2.0
  • ABI:
Free Pascal
Nim
  • Maintainer(s): Andreas Rumpf and others
  • Version: 0.18.1
  • Status: Initial support added
  • RISC-V repository: same as upstream
  • Upstream repository: https://nim-lang.org/
Forth kernels

muForth

lbForth

  • Maintainer(s): Lars Brinkhoff
  • Version:
  • Status:
  • Upstreaming status: N/A
  • Future work:
  • RISC-V repository: N/A
  • Upstream repository: https://github.com/larsbrinkhoff/lbForth
  • Privileged Spec:
  • User Spec: 2.0
  • ABI: N/A

Mecrisp-Quintus

Ada (GNAT)

IDEs

GNU MCU Eclipse

An open source project that includes a family of Eclipse plug-ins and tools for multi-platform embedded development, based on GNU toolchains; includes support for RISC-V.

Help Wanted

  • V8
  • Node.js
  • Dart
  • Rust