Our 4th RISC-V Workshop will be hosted by MIT in Cambridge, MA, July 12-13, 2016. The Workshop final agenda is shown below. We are sold out and registration is now closed.
About the Workshop
The goals for our RISC-V workshops are for the community to share information about recent activity in various RISC-V projects underway around the globe, and to build consensus on future steps with the RISC-V ISA. This workshop features talks and poster presentations conveying recent activity in the RISC-V community at large, collected during an open submission period.
Preliminary Agenda
Tuesday, July 12th, 2016
| Time | Event | Speaker, Affiliation | Media |
| 8:00am | Networking Breakfast | ||
| 8:30am | Workshop Logistics and RISC-V Foundation Update | Rick O’Connor, RISC-V | |
| 9:00am | RISC-V Interrupts | Krste Asanović, UC Berkeley & SiFive Inc. | |
| 9:30am | Formal Specification of RISC-V Uniprocessor Consistency | Arvind, MIT | |
| 10:00am | Heterogeneous Multicore RISC-V Processors in FD-SOI Silicon | Thomas Peyret, CEA Tech | |
| 10:30am | Networking Break | ||
| 11:00am | NVIDIA RISC-V Evaluation Story | Joe Xie, NVIDIA | |
| 11:30am | ISA Shootout – a Comparison of RISC-V, ARM, and x86 | Chris Celio, UC Berkeley | |
| 12:00pm | Trace Debugging in lowRISC | Wei Song, University of Cambridge | |
| 12:30pm | Networking Lunch | ||
| 1:30pm | RISC-V I/O Scale Out Architecture for Distributed Data Analytics | Mohammad Akhter, IDT | |
| 2:00pm | Coherent Storage: Brave New World of Non-Volatile Main Memory | Dejan Vucinić, Western Digital | |
| 2:30pm | RISC-V as basis for ASIP Design – an IoT Security Example | Dan Ganousis, Codasip Drake Smith, Secure RF | |
| 3:00pm | An Update on Building the RISC-V Software Ecosystem | Arun Thomas, BAE Systems | |
| 3:15pm | ORCA-LVE: Embedded RISC-V with Lightweight Vector Extensions | Guy Lemieux, VectorBlox | |
| 3:30pm | Networking Break & Breakout Sessions | ||
| 4:00pm | FPGArduino: A Cross-Platform RISC-V IDE for masses | Marko Zec, University of Zagreb | |
| 4:15pm | SiFive’s RISC-V computer: An open software development platform for RISC-V SoCs | Jack Kang, SiFive | |
| 4:30pm | 18 Poster / Demo Previews ~ 3min per presenter | ||
| 5:30pm | Leave to walk over to the Google facility at 355 Main St. | ||
| 6:00pm | Networking Reception, Posters Sessions & Demos | Hosted at Google, 355 Main St. | |
| 8:00pm | Adjourn for the Day |
Wednesday, July 13th, 2016
| Time | Event | Speaker, Affiliation | Media |
| 8:00am | Networking Breakfast | ||
| 8:30am | Riscy Processors – A Collection of Open-Sourced RISC-V Processors | Andy Wright, MIT | |
| 9:00am | SW Programmable FPGA IoT Platform: RISC-V Processor with Auto-Generated HW Accelerators | Andrew Canis, LegUp Computing | |
| 9:30am | Apache Mynewt: The Next Great Open Source OS for 32-Bit MCUs. Coming soon to a RISC-V MCU near you! | James Pace, Runtime | |
| 10:00am | DSP ISA Extensions for an Open-Source RISC-V Implementation | Pasquale Davide Schiavone, ETH Zurich | |
| 10:15am | The DOVER Edge: A Metadata-Enhanced RISC-V Architecture | Andre DeHon, DRAPER Labs | |
| 10:30am | Networking Break & Group Photo | ||
| 11:00am | Improving The Performance Per Area Factor of RISC-V Based Multi-Core Systems | Tobias Strauch, EDAptix | |
| 11:15am | Working Towards a Debian RISC-V Port | Manuel A. Fernandez Montecelo | |
| 11:30am | Kami: A Framework for RISC-V HW Verification | Murali Vijayaraghavan, MIT | |
| 11:45pm | 4th RISC-V Workshop Wrap Up | Rick O’Connor, RISC-V Foundation | |
| 12:00pm | Networking Lunch (Workshop Ends) | ||
| 1:00pm | Hands On RISC-V Tutorial (separate advanced registration required) | ||
| 6:00pm | Tutorial Ends |