7th RISC-V Workshop Preliminary Agenda

7th RISC-V Workshop Preliminary Agenda

November 28-30, 2017

Our preliminary agenda is posted below and registration for the 7th RISC-V Workshop, hosted by Western Digital in Milpitas California on November 28-30, 2017 is now closed as the workshop is now sold out.

Our goals for these events are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build consensus on the future evolution of the instruction set.

This will be a three day event broken down as follow:

  • Tuesday and Wednesday November 28-29, 2017 – These two days will follow our traditional two day format used at previous workshops with presentations covering various RISC-V projects underway within the RISC-V community and will include a poster / demo reception on Tuesday evening.
  • Thursday November 30, 2017 – The workshop week will conclude with RISC-V Foundation meetings with attendance restricted to members of the RISC-V Foundation.  The day will consist of Technical and Marketing Committee face to face meetings to progress the work currently underway within our various Task Groups.

Each workshop has helped both document the rapidly rising popularity of RISC-V and boosted it further due to the information shared and collaborations formed at the event.

Preliminary Agenda

Tuesday, November 28th, 2017 7th RISC-V Workshop Day 1

Time Event Speaker, Affiliation Media
8:00am Registration and Networking Breakfast
RISC-V Update
8:45am 7th RISC-V Foundation Update and Workshop Introduction Rick O’Connor, RISC-V Foundation
9:00am RISC-V State of the Union Krste Asanovic, UC Berkeley
9:42am RISC-V Hypervisor Extensions Andrew Waterman, SiFive
9:54am RISC-V Memory Consistency Model Status Update Daniel Lustig, NVIDIA
10:18am Networking Break
Keynote Address
10:48am Keynote: RISC-V – The Accelerator of Data Insights Martin Fink, Western Digital
Commercial RISC-V Implementations
11:36am Industrial strength high-performance RISC-V processors for energy efficient computing David Ditzel, Esperanto Technologies
12:00pm Andes Extended RISC-V Features Chuan-Hua Chang, Andes Technology
12:12pm Customization of a RISC-V Processor to Achieve DSP Performance Gain Marcela Zachariasova, Codasip
12:24pm Freedom U500, a Linux-capable, 1.5GHz quad-core RV64GC based SoC Jack Kang, SiFive
12:36pm Revolutionizing RISC-V based application design possibilities with Global Foundries Sanjay Charagulla, Global Foundries
12:48pm Networking Lunch
RISC-V Software Ecosystem
1:48pm RISC-V LLVM: Towards a production-ready LLVM-based toolchain Alex Bradbury, lowRISC
2:12pm A RISC-V Java Update: Running Full Java Applications on FPGA-based RISC-V Cores with JikesRVM Martin Maas, UC Berkeley
2:24pm MicroProbe: An Open Source Microbenchmark Generator Ported to the RISC-V ISA Schuyler Eldridge, IBM Watson Research Center
2:48pm RISC-V Debug Support by Lauterbach TRACE32 Bob Kupyn, Lauterbach
3:00pm J-Link – professional debug probe now available for RISC-V Rolf Segger, SEGGER
3:12pm Porting the ThreadX RTOS to RISC-V John Carbone, Express Logic
3:24pm Networking Break
RISC-V Architecture
3:54pm xBGAS: A Bridge Proposal for RV128 and HPC John Leidel, Tactical Computing Laboratories
4:06pm The case for expanding the 16 GPR standard beyond RV32E Mitchell Hayenga, Revolution Computing
4:18pm Using Pyrope to Create Transformable RISC-V Architectures Haven Skinner, UC Santa Cruz
4:30pm Performance Isolation for Multicore within Labeled RISC-V Zihao Yu, ICT CAS
4:42pm A Practical Implementation of a Platform Level Interrupt Controller (PLIC) Richard Herveille, Roa Logic
4:54pm RTOS Ports on Microsemi’s RISC-V processor for IoT and embedded applications Nitin Deshpande, Microsemi
5:06pm Poster / Demo Previews ~ 2min per presenter
Taking RISC-V to new heights Cyril Jean, Microsemi
End-to-end formal ISA verification of RISC-V processors with riscv-formal Clifford Wolf, Symbiotic EDA
Design of a Generic Security Interface for RISC-V Processors and its Applications Hyunyoung Oh, SOR Lab, Seoul National University
ChiselFlow: A Hardware Description Language for Information Flow Security Embedded in Chisel Andrew Ferraiuolo, Cornell
MicroPython Port for Microsemi’s RISC-V soft Processor Badal Nilawar, Microsemi
A Free RISC-V CPU meets a commercial Real Time Operating System Matt Gordon, Silabs
Enabling Safe Crypto using RISC-V Soft Processor Sathish Kumar Odiga, Microsemi
RISC-V based Lockstep Processor Implementation Sathish Kumar Odiga, Microsemi
An Engines Instruction Set Extension for the RISC-V Architecture Eric McCorkle, Metricspace
Taiga: a RISC-V Soft-Processor for FPGA-Based Heterogeneous Systems Research Eric Matthews, Simon Fraser University
Cloud-Based RISC-V SoC design and Co-simulation Mohamed Shalan, American University Cairo
DBT-RISE: Addressing the RISC-V Virtual Platform Challenge Eyck Jentzsch, Minres
Detecting Advanced Malware as Instruction- and μ-architectural Anomalies Pranav Kumar, University of Texas
Comparison of two RISC-V JIT compiler approaches Boris Shingarov Labware
FPGA-based CNN Hardware Accelerator with RISC-V Processor Marcela Zachariasova Codasip
RIOT IoT OS Port to RISC-V Craig Steele, Tautline
SCR cores extensibility overview Alexander Redkin, Syntacore
BESSPIN and SSITH Joseph Kiniry, Galois
Experiments in RISC-V Trusted Boot Joseph Kiniry, Galois
Live Demo for RISC-V Debug Support by Lauterbach TRACE32 Bob Kupyn, Lauterbach
Imperas and Microsemi Collaborate on Commercially Supported RISC-V ISS and Platform Development Tools Simon Davidmann Imperas
How to Secure RISC-V Processors Julian Scherding, Dover Microsystems
RISC-V Compliance Task Group Update Marcela Zachariasova, Codasip
RISC-V Software Task Group Update Arun Thomas, BAE Systems
RISC-V Educational Literature Dave Patterson
RISC-V Core IP Demos: Debugging, RTOS, and Linux! Jack Kang, SiFive
6:00pm Networking Reception, Posters Sessions and Demos
9:00pm Adjourn for the Day

Wednesday, November 29th, 2017 7th RISC-V Workshop Day 2

Time Event Speaker, Affiliation Media
8:00am Networking Breakfast
Open Source RISC-V Implementations
9:00am Celerity: An Open Source 511-core RISC-V Tiered Accelerator Fabric Michael Taylor, University of Washington
9:24am The PULP Cores: A Set of Open-Source Ultra-Low-Power RISC-V Cores for Internet-of-Things Applications Pasquale Davide Schiavone, ETH Zurich
9:36am BOOM v2: an open-source out-of-order RISC-V core Christopher Celio, UC Berkeley
10:00am Rocket Engines: Low-Effort Design Reuse in RISC-V Implementations Albert Magyar, Google
10:12am Networking Break
Keynote Address
10:42am Keynote A Perspective on the Role of Open-Source IP in Government Electronic Systems Linton Salmon,DARPA
Open Source RISC-V Silicon
11:30am Boosting RISC-V ISA with Open Source Peripherals: An SoC for Low Power Sensors Elkim Roa, Onchip
11:42am PicoSoC: How we created a RISC-V based ASIC processor using a full open source foundry-targeted RTL-to-GDS flow, and how you can, too! Tim Edwards, efabless Corporation
11:54am TileLink: A free and open-source, high-performance scalable cache-coherent fabric designed for RISC-V Henry Cook, SiFive
12:18m Free Chips Project (FCP) Update Yunsup Lee, FCP
12:30pm Networking Lunch
RISC-V Vectors and Security
1:30pm RISC-V V Vector Extension proposal Roger Espasa, Esperanto Technologies
1:54pm Security task group update and RISC-V security extension Joe Xie, NVIDIA
2:18pm Using Proposed Vector and Crypto Extensions For Fast and Secure Boot Richard Newell, Microsemi
2:30pm Using RISC-V as a Security Processor for DARPA CHIPS and Commercial IoT Mark Beal, Intrinsix
2:42pm ISA Formal Task Group Update Rishiyur Nikhil, Bluespec
2:54pm Strong Formal Verification for RISC-V: From Instruction-Set Manual to RTL Adam Chlipala, MIT
3:18pm Networking Break
RISC-V Applications / Accelerators
3:48pm Work in Progress Update: GRVI Phalanx.2 on Amazon AWS EC2 F1: Ploughing 1 TB of RAM with Twenty x86 Oxen and 10,000 RISC-V Chickens Jan Gray, Gray Resesarch LLC
4:00pm A Tightly-coupled Light-Weight Neural Network Processing Units with RISC-V Core Lei Zhang, ICT CAS
4:12pm A RISC-V Based Linear Algebra Accelerator for SoC Designs Samuel Steffl, Brown University
4:24pm Packet Manipulator Processor: A RISC-V VLIW core for networking applications Marco Spaziani Brunella, CNIT University of Rome Tor Vergata
4:36pm Adding a Binarized CNN Accelerator to RISC-V for Person Detection Guy Lemieux, VectorBlox
RISC-V Simulation Infrastructure
4:48pm RISC5: Improving Support for RISC-V in gem5 Alec Roelke, University of Virginia
5:00pm Renode: a flexible, open-source simulation framework for building scalable, well-tested RISC-V systems Michael Gielda, Antmicro
5:12pm QEMU-based Hardware Modeling of a multi-hart RISC-V based FPGA with Execution Contexts free from Interference Daire McNamara, Emdalo Technologies
5:24pm FireSim: Cycle-Accurate Rack-Scale System Simulation using FPGAs in the Public Cloud Sagar Karandikar, UC Berkeley
5:48pm 7th RISC-V Workshop Wrap Rick O’Connor, RISC-V Foundation
6:00pm End of Workshop

Thursday, November 30th, 2017 RISC-V Foundation Member Meetings

(detailed agenda to be announced)

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