Andes Technology announced that the AndeStarTM V5 CPU processor cores N25/N25F, NX25/NX25F, A25 and AX25 have the Andes Custom ExtensionTM (ACE) function. Andes Technology will develop embedded processor IP with more than ten years of experience combined with RISC-V technology, launching AndeStarTM V5 architecture, and now further ACE, making it easier for embedded system engineers to add custom-made system to the Andes Technology V5 processor instructions.
RISC-V is an open source instruction set architecture (ISA) developed by the non-profit RISC-V Foundation. Because RISC-V has the advantages of streamlining, modularization and scalability, it has recently emerged in various important application fields. In addition to its general functionality, the RISC-V specification reserves the space for custom instruction sets to facilitate the addition of Domain-Specific Architecture/Acceleration (DSA) extensions to support applications such as artificial intelligence/machine learning, AR/VR, ADAS and designed for generations of storage and networking. Customized instructions greatly enhance application performance while maintaining programmability. However, designing new instructions requires CPU expertise and a lot of manpower to modify existing processor hardware and related software tools, and to confirm that their functionality is correct, so adding custom instructions is not easy for many SoC design teams.
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