UltraSoC Extends On-Chip Analytics Architecture For The Age Of Machine Learning, Artificial Intelligence And Parallel Computing

UltraSoC today announced a significant extension of its embedded analytics architecture, allowing designers and innovators to incorporate powerful data-driven features into their products. Developers in the automotive, storage and high performance computing industries can now integrate even more sophisticated hardware-based security, safety and performance tuning capabilities within their products, as well as reaping substantial time-to-market and cost benefits of using UltraSoC in the system on chip (SoC) development cycle.The new…

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GOWIN Semiconductor To Participate St Embedded World 2019

GOWIN Semiconductor Corp., the world’s leading innovator of programmable logic devices, will exhibit at Embedded World 2019 on February 26-28 in Nuremberg, Germany, showcasing their latest FPGA technology to the European market. They will be located in the Eldis booth, Hall 3A Stand 708.Embedded World, held annually in Germany, is Europe’s leading trade show for all embedded solutions and technologies. With over 1000 exhibitors, it is one of the world’s…

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AnandTech Article: Western Digital’s RISC-V “SweRV” Core Design Released For Free

Western Digital has published a register-transfer level (RTL) design abstraction of its in-house designed SweRV RISC-V core. The SweRV core is one of several RISC-V projects the company as undertaken as part of their effort to spearhead the ISA, its ecosystem, and foster their own transition away from licensed, royalty-charging CPU cores. In accordance with the more open design goals of RISC-V, the publication of the high-level representation of SweTV means…

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Hackaday Article: New Part Day: A RISC-V CPU For Eight Dollars

RISC-V is the new hotness, and companies are churning out code and announcements. Eventually, RISC-V microcontrollers and SoCs will cost just a few bucks. This day might be here, with Seeed’s Sipeed MAix modules. it’s a RISC-V chip you can buy right now, the bare module costs eight US dollars, there are several modules, and it has “AI.”Those of you following the developments in the RISC-V world may say this chip…

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EBN Article: Open Source Hardware Benefits Procurement Practices

Electronics engineers and designers will enjoy a variety of benefits of the advent of processor options based the RISC-V Instruction Set Architecture (ISA). The supply chain and procurement department, though, has the potential of capturing a variety of sourcing benefits related to the nature of open source offerings as well.“Open source does two things for you: it rationalizes price and motivates adoption and investment,” explained Keith Witek, senior vice president,…

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EE Times Article: SiFive Sees Big Year For RISC-V

If Naveed Sherwani gets his way, 2019 will be a year to remember for his startup, SiFive, the RISC-V architecture, and maybe even the whole semiconductor industry.By the end of the year, SiFive could have cores that span the range of its entrenched rival Arm, said Sherwani, who in late 2017 was named CEO of the startup founded by RISC-V creators at Berkeley. This year, all RISC-V companies together could…

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EE Times Article: RISC-V Climbs Software Mountain

Now that RISC-V has established a beachhead as a deeply embedded controller in SoCs, it’s time to start asking the next question: Can this open-source instruction-set architecture (ISA) make the next big leap into being an alternative to Arm and the x86 as a host processor?The short answer is yes, but it could take several years and there are plenty of pitfalls along the way. Essentially, the freewheeling open-source community…

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EDN Article: Creating A Custom Processor With RISC-V

With its blend of open-source freedoms with the benefits of standardization, the RISC-V (risk-five) Foundation is attracting widespread industry interest. Its core specifications are stable and on the cusp of ratification, soft- and hard CPU cores along with chips, development boards, and tools are commercially available, and major companies have started adopting RISC-V to replace their custom architectures. A key feature in the architecture’s appeal is that CPU developers can…

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EE Times Article: RISC-V On The Verge Of Broad Adoption

There are major hurdles to overcome when bringing a new processor architecture to market. Today’s fast-paced development practices demand that processor offerings be stable with the promise of a long market lifetime. Further, they must come to market with substantial support in the form of development tools, software libraries, operating systems, emulators, debuggers, and more. The emerging RISC-V instruction set architecture has faced and is overcoming those hurdles and is…

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Military And Aerospace Electronics Article: AdaCore And NVIDIA Team On Ada And SPARK Programming Languages For Safety-Critical Software

Software specialist AdaCore in New York is working with NVIDIA Corp. in Santa Clara, Calif., to implement the Ada and SPARK programming languages for security- and safety-critical firmware in applications like avionics and self-driving cars.Some NVIDIA system-on-a-chip product lines will migrate to a new architecture using the RISC-V instruction set architecture (ISA). Also, NVIDIA plans to upgrade security-critical firmware software, rewriting it from C to Ada and SPARK. To read more,…

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