WHO: Andes Technology Corporation, the leading Asia-based supplier of small, low-power, high performance 32/64-bit embedded CPU cores, today announced that it will present in the TSMC OIP Theater during the 2018 Design Automation Conference. The company will exhibit its latest RISC-V CPU IP cores in booth 2658.WHAT: Andes Technology Corporation Field Application Engineer, I-Tao Tsai will present” Taking RISC-V to Mainstream ASICs.”WHEN: Andes FAE I-Tao Tsai will present Monday June 25th from 3:15pm…
Read More...Electronics Weekly Article: UltraSoc Links With Imperas
UltraSoC will incorporate key elements of Imperas’ development environment into its tools offering, giving designers a unified system-level pre- and post-silicon development flow, dramatically reducing time-to-revenue and overall development costs.UltraSoC delivers the industry’s leading independent on-chip monitoring, analytics and debug technology, via a combination of semiconductor IP and associated software. Imperas’ virtual platforms approach allows software developers to start work at the earliest possible stage in an SoC project.Combining the…
Read More...UltraSoC Embedded Analytics And Imperas Virtual Platforms Combine To Enhance Multicore Development And Debug
UltraSoC and Imperas today announced a wide-ranging partnership that will provide developers of multicore systems on chip (SoCs) with a powerful combination of embedded analytics and virtual platform technologies. Under the terms of the agreement, UltraSoC will incorporate key elements of Imperas’ development environment into its tools offering, giving designers a unified system-level pre- and post-silicon development flow, dramatically reducing time-to-revenue and overall development costs.UltraSoC delivers the industry’s leading independent on-chip monitoring, analytics…
Read More...Andes Certifies Imperas Models And Simulator As A Reference For Andes RISC-V Cores
Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, and Andes Technology Corporation, the prominent CPU IP provider, today announced that Andes has certified the Open Virtual Platforms™ (OVP™) instruction-accurate models and virtual platforms of the AndesCore™ N25 and NX25 IP processors. This rigorous certification program by Andes involves simulation and testing to their highest standard of accuracy, using a variety of real-world test cases and proprietary methods….
Read More...RISC-V Workshop in Chennai
RISC-V Workshop in Chennai July 18-19, 2018 The RISC-V Foundation invites you to attend the RISC-V Workshop in Chennai, India on July 18-19, 2018. Hosted by The Indian Institute of Technology Madras (IIT Madras) and sponsored by Western Digital, the RISC-V Workshop in Chennai will discuss current and prospective RISC-V projects and implementations, as well as influence the future evolution of the instruction set architecture (ISA) from Silicon Valley to…
Read More...RISC-V Ecosystem Highlights Momentum Across Asia At RISC-V Day In Shanghai
RISC-V members to present on RISC-V based products and solutionsWHERE: Fudan University, Handan Campus, 220 Handan Rd, WuJiaoChang, Yangpu Qu, Shanghai Shi, China, 200433WHEN: Saturday, June 30, 2018, 8 a.m. – 6 p.m. CSTWHAT: The RISC-V Foundation will share updates on new projects and implementations from its international membership at the RISC-V Day in Shanghai, with a focus on the growth of the RISC-V ecosystem across Asia. RISC-V Foundation member…
Read More...Dolphin Integration Makes Available In Free Download Its Innovative IDE SmartVision, For The RISC-V Ecosystem
Dolphin Integration announces the availability in free download of its innovative IDE SmartVision™ supporting the RISC-V Instruction Set Architecture (ISA).A suitable software development environment is fundamental for optimizing designs in terms of power consumption, area (code density) and performances. Thanks to its IDE, Dolphin integration enables early in the design flow to meet these requirements.SmartVision™ is an open environment allowing the design of complete subsystems based on processor cores and peripherals. It provides an intuitive…
Read More...RISC-V Day in Shanghai
RISC-V Day in Shanghai June 30, 2018 The RISC-V Foundation invites you to attend RISC-V Day in Shanghai, China on June 30, 2018. Hosted by Fudan University in Shanghai, the event will include in-depth technical presentations and updates on the RISC-V architecture, a speaking lineup from leading technology companies and research institutions in the RISC-V ecosystem and ample opportunity for networking.The RISC-V Day in Shanghai agenda will be categorized into the…
Read More...RISC-V Summit – Call for Papers
Call for Papers RISC-V Summit December 3-6, 2018 Lead Sponsor: We’re seeking proposals for speaking sessions that explore recent developments in the RISC-V community at the inaugural RISC-V Summit, held at the Santa Clara Convention Center in Santa Clara, Calif. from Dec. 3-6, 2018.The speaking faculty and program are selected based on the topic and content submitted and the speaker’s qualifications by the program committee and the RISC-V research and editorial…
Read More...Growing RISC-V Ecosystem To Share New Developments And Momentum At DAC 2018
RISC-V Foundation and members to exhibit and participate in a variety of speaking tracksWHERE: DAC 2018, West Hall, Level Two at Booth #2638; Moscone Center West, 800 Howard St, San Francisco, CA 94103WHEN: Sunday, June 24 to Wednesday, June 27, 2018WHAT: The RISC-V Foundation will share updates on new projects, products and implementations from its expansive membership at DAC 2018. The RISC-V Foundation will be exhibiting with member companies Imperas…
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