In the News

Dr. Krste Asanovic, co-inventor of RISCV and co-founder of SiFive, tells the tale of how RISC-V came into being, and what the vision for SiFive is, for the IEEE Custom...

SEGGER announces a new version of the RISC-V Floating-Point Library with full support for RV32E – the embedded variant of the RISC-V core. The new library leads to a massive...

Industry Veteran To Lead Mission To Develop RISC-V-based Platforms to Solve Next-Generation Computing Challenges Read the full article here and here.

In this press release, Microchip announced the industry’s first RISC-V-based System-on-Chip (SoC) Field-Programmable Gate Array (FPGA) development kit for PolarFire SoC FPGA—the industry-leading low-power, low-cost, RISC-V-based SoC FPGA. Microchip’s Icicle...

Getting down to the nitty gritty an analyst asked: "Would a combined Nvidia-ARM continue to develop ARM's Mali graphics processor architecture and continue to use the RISC-V processor architecture?" Huang...

Haskell and Python, languages that probably do not spring to mind when you think of languages that let you get down to the “Bare Metal” of your computer… But they...

Our 3rd report from the RISC-V Global Forum, September 3, 2020. We start with RISC-V in China, where RISC-V offers opportunities for IoT, the we have a look at whether...

0:00 Introduction 1:37 The case of the phantom packets 8:07 A bug free RISCV core without simulation 14:23 Under the hood of formal verification:  Follow Tom on twitter: https://twitter.com/tom_verbeure Tom's...

Our second report from the RISC-V Global Forum, September 3, 2020. In this report we talk about the very big and the very small. The European Space Agency (ESA) is...