SiFive Inc. (San Francisco, Calif.) has created a global network of nine startup companies to help support design wins for the RISC-V instruction set architecture. It is pretty easy to see what SemiFive, StarFive and LeapFive all have in common with SiFive but as SiFive CEO Naveed Sherwani explained on Linkedin they are just three of a set of nine companies around the world affiliated to SiFive and all started…
Read More...Upcoming SAVVY-V Open Source RISC-V Cluster Board Supports 10GbE via Microsemi PolarFire 64-bit RISC-V SoC | Jean-Luc Aufranc, CNX Software
Upcoming SAVVY-V Open Source RISC-V Cluster Board Supports 10GbE via Microsemi PolarFire 64-bit RISC-V SoC
Read More...Security and Trust Assurance of RISC-V Open-Source Cores RocketCore: Sven Beyer | McKenzie Ross, OneSpin Solutions
RISC-V Forças e Fraquezas | Rogerio Moreira, Embarcados TV
BoF: Open Hardware and RISC-V – Drew Fustini & Stephano Cetola
Design an Open-Source SoC with Google SkyWater PDK, Get It Manufactured for Free | Jean-Luc Aufranc, CNX Software
Design an Open-Source SoC with Google SkyWater PDK, Get It Manufactured for Free
Read More...Improving RISC-V Linux Support in Rust | Tom Eccles, Codethink
RISC-V is a new Instruction Set Architecture developed in the open and available for use without paying a license fee. Being an open ISA means there are no barriers to achieving open hardware implementations – which opens the door to performant (mostly) open hardware processors!Article: https://www.codethink.co.uk/articles/2020/improving-risc-v-linux-support-in-rust/
Read More...Fixing Rust’s Test Suite on RISC-V | Tom Eccles, Codethink
My previous blog post introduced my work to improve Rust’s support for RISC-V Linux systems. Since then I fixed a couple of interesting compiler bugs. This blog post is more technical – describing these bugs and explaining some rustc internals along the way. I conclude by reporting on movement in the broader Rust community regarding RISC-V. I assumed that the reader is comfortable with programming terminology. This blog post contains Rust code samples but the reader is not…
Read More...DAC 2020 Preview: Interest In AI, Ml And RISC-V Grow To New Levels This Year | Nitin Dahad, EE Times
This year, the 57th Design Automation Conference (DAC) was all set to take place at the Moscone Center in San Francisco. But then, as with many other conferences around the world, the enforced lockdown resulting from Covid-19 meant the DAC executive committee had no choice but to make this year’s conference a virtual experience.In order to give you a taste of what to expect this year, we talked to program track…
Read More...Software Analysis: Use Trace Techniques Efficiently for RISC-V | Robert Chyla & Thomas Andersson
Trace techniques allow the programmer a comprehensive insight into the application. This allows you to track every single instruction and see whether your application is running as intended or whether there are errors or weak points.Article: https://www.all-electronics.de/softwareanalyse-trace-techniken-effizient-einsetzen-fuer-risc-v/
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