Semiconductor supplier GigaDevice introduced the GD32V General Purpose RISC-V MCU based on the open-source instruction–set architecture RISC-V. The RISC-V microcontroller unit supports the standard JTAG interface and RISC-V debug standards, as well as the RISC-V standard build toolchain. Additionally, it supports a Linux/Windows graphical integrated development environment. To read more, please visit https://www.cnbeta.com/articles/tech/881519.htm. Please note that the original article is in Chinese.

The European Processor Initiative(EPI) project includes experts in the silicon and High-Performance Computing (HPC) industries are collaborating to develop the first European HPC system-on-chips (SoCs) and accelerators, with the goal of creating a processor for the Exascale machine based on European technology. The EPI consortium includes RISC-V Foundation members Barcelona Supercomputing Center (BSC), CEA, ETH Zurich, FORTH, Infineon, and STMicroelectronics. To read more, please visit https://insidehpc.com/2019/08/how-the-european-processor-initiative-is-leveraging-risc-v-for-the-future-of-supercomputing/.

A custom processor has grown to mean that processors are now optimized for a particular class of tasks. The microarchitecture and instruction set is informed by the software it ultimately will run. Today, demand is high for customization tools that can realize proprietary instruction extensions of a standard ISA. The RISC-V Foundation has contributed greatly to the customization as its modular architecture provides space for non-standard extensions and proprietary software…

Andes Technology‘s RISC-V architecture, Zhizhicai, has the advantages of customization and low cost, making an annual revenue close to 200 times its competitors. There are two reasons for this company’s success – One is the policy change after Softbank’s acquisition; the other is that the RISC-V architecture is becoming a replacement for its architecture processor.Compared to the IPO processor architecture, RISC-V has the advantage of providing more flexibility and openness,…

Western Digital, best known to most as a seller of hard drives, has gone all-in on open source. While not a stranger to open source software, and far from being the first hardware company to embrace open-source — it recently became a pioneer by diving headfirst into the uncharted waters of open source silicon. It seems fitting for a company that started in the 1970s as a chipmaker.The baby steps…

As of July this year, the RISC-V Foundation has attracted 178 companies and research institutions to join, with more than 327 members, from 28 countries around the world. Covering 52 percent of the world’s population, the Foundation continues to expand and represents a variety of enterprises, research institutions, and universities from Greater China/ Prior to the advent of RISC-V, a variety of instruction set architectures (ISAs) have emerged in history. To…

Lauterbach, a Silver Member of the RISC-V Foundation, has announced full JTAG debug support for Linux running on systems based on the RISC-V Open Source ISA.The Linux kernel awareness integrates with the TRACE32 debugger providing users with a seamless debugging experience across the entire system life cycle, from board bring-up to task level debugging. This allows for a single tool to be used in all phases of system development and…

Gary Sims of Gary Explains comes on the show to talk about open-sourced hardware and some of the myths that surround the RISC-V ISA. Is this the Linux version of hardware that we’ve all been waiting for? Gary has a few things to say about that. Want to know what goes into designing a chip? To listen to the full podcast, please visit http://podcasts.androidauthority.com/gary-explains-risc-v-the-open-sourced-hardware-solution-of-our-dreams.

Red Hat, a well-known enterprise open-source software and solution provider acquired by IBM, joined the RISC-V Foundation. At the end of last year, the RISC-V Foundation and the Linux Foundation announced its partnership. The cooperation between open-source hardware and open-source software giants marks the introduction of an era of open-source hardware.RISC-V is streamlined open-source, and free. The architecture separates the reference instruction from the extended instruction. There are only a…

NTX is the name given to a hardware accelerator that ETH Zurich has developed for floating-point arithmetic. With 260 Gflops / W, the chip implemented in 22nm FD-SOI offers unmatched energy efficiency and beats every competitor by far.  Eight NTX units are controlled by an RV32IMC RISC V-Core, which provides full software flexibility. A key feature is a focus on eliminating the bottleneck common to Neumann architectures by amortizing RISC-V instructions…