CHANDLER, Ariz. – Microchip Technology Inc. in Chandler, Ariz., is opening the Early Access Program (EAP) for the PolarFire field programmable gate array (FPGA) system-on-chip (SoC).The platform offers a hardened real-time, Linux capable, RISC-V-based microprocessor subsystem on the mid-range PolarFire FPGA family for applications that require low power consumption, thermal efficiency, and defense-grade security in embedded computing systems.article: https://www.militaryaerospace.com/computers/article/14074714/embedded-computing-fpga-lowpower

This piece talks about more of the storage and memory products and applications on display in exhibits and suites at the 2020 CES.  In particular we will discuss SK hynix, Kingston, Gigabyte, OWC, Macronix and Quantum products and storage applications on display at the show.article: https://www.forbes.com/sites/tomcoughlin/2020/01/13/storage-and-memory-at-the-2020-ces-part-2/#6a21b31d4052

Domain-specific accelerators (DSAs) are becoming increasingly common in systems-on-chip (SoCs). A DSA provides higher performance per watt than a general-purpose processor by optimizing the specialized function it implements. Examples of DSAs include compression/decompression units, random number generators and network packet processors. A DSA is typically connected to the core complex using a standard IO interconnect, such as an AXI bus.article: https://www.sifive.com/blog/fast-access-to-accelerators-enabling-optimized-data-transfer-with-risc-v

 article: https://www.itworldcanada.com/blog/bleeding-edge-information-technology-developments/425631

A Look At Celerity’s Second-Gen 496-Core RISC-V Mesh NoC

Hsinchu, Taiwan – January 09, 2020 – Andes Technology (TWSE: 6533), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores, has cooperated with more than 70 universities worldwide to date, after signing the first contract of industry-academia cooperation with National Chiao Tung University (NCTU) in 2010. Andes continues to provide CPU IP AndesCore™ licensing, software development tool AndeSight™, and hardware development platforms to schools with licensing series from AndeStar V3 architecture to…

Designers are under constant pressure to innovate yet keep their intellectual property (IP) secret, while also lowering power consumption and cost. This made the RISC-V open-source hardware instruction set architecture (ISA) interesting for designers of processors for mobile applications. Now that RISC-V is an option for microcontrollers, designers of embedded systems and consumer devices need a quick on-ramp to start their own RISC-V designs.article: https://www.digikey.com/en/articles/techzone/2020/jan/how-to-get-started-with-risc-v-based-microcontrollers

SiFive and CEVA announced that CEVA-BX audio DSPs, CEVA-XM vision chips, and up to 12.5-TOPS NeuPro AI processors will be added to SiFive’s DesignShare program, enabling customers to create custom “Edge AI SoCs” built around SiFive’s RISC-V CPUs.article: http://linuxgizmos.com/build-your-own-edge-ai-soc-with-sifive-risc-v-cpus-and-ceva-neural-coprocessors/

SiFive, one of the best known providers of RISC-V processor IP, has partnered with Ceva, a leading provider of embedded chip solutions, to create embedded AI processors for the mainstream market using the RISC-V instruction set architecture (ISA).article: https://www.tomshardware.com/news/sifive-and-ceva-partner-to-build-mainstream-edge-ai-processors

ONiO.zero offers a RISC-V Microcontroller that runs without battery