jqknews Article: Turing Award Winners Lead Tsinghua And Berkeley To Build RISC-V International Open Source Laboratory

As a world-renowned top scientist in the field of computer architecture, David Patterson first proposed the Reduced Instruction Set (RISC) system. The Fifth Generation Reduced Instruction Set (RISC-V) is the latest generation of Berkeley RISC processor instruction set, which was first released in 2011 by the University of California team led by Professor Patterson. The development of RISC-V hardware and software technology has attracted worldwide attention.In particular, the instruction set…

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cnBeta Article: Berkeley And Tsinghua Establish RIOS Laboratory; RISC-V Is Expected To Upgrade To The Most Advanced Level

UC Berkeley honorary professor David Patterson announced at the RISC-V Summit that he will establish a RISC-V International Open Source Laboratory (RIOS Laboratory) dedicated to RISC-V research. The laboratory is located at the Tsinghua-Berkeley Shenzhen Institute (TBSI) jointly established by the University of California at Berkeley and Tsinghua University.Professor David Patterson is the first expert to propose the “Reduced Instruction Set” (RISC) system. He is currently an honorary professor at the…

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ScienceNet Article: Turing Award Winners Build RISC-V International Open Source Lab

On June 12th, the Pardee Honorary Professor of the University of California Berkeley School of Arts and Science and winner of the 2017 Turing Award David Patterson announced the RISC-V International Open Source Laboratory. The laboratory is also known as the David Patterson RIOS Turing Award Lab (hereinafter referred to as RIOS Lab).As the world’s top scientist in the field of computer architecture, David Patterson first proposed the “Reduced Instruction…

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KIPOST Article: Open Source Architecture RISC-V At A Glance … Cy5 Five Technology Symposium

The open source “RISC-V” Instruction Set Architecture (ISA) is one of the latest trends in the semiconductor industry. SiFive, the semiconductor design firm that leads the RISC-V architecture ecosystem, will host the first technology symposium in Korea.On May 17, Saipaek Korea announced that it will hold the ‘2019 SiFive Technology Symposium’ at the Pangyo Semiconductor Industry Association Hall on May 17 at Daejeon KAIST Academic Cultural Center.Saifev was founded by…

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My Drivers Article: NVIDIA Also Looks At The RISC-V Architecture: Incorporating Deep Neural Network Accelerators

With its open features, the RISC-V architecture and instruction set are gaining more and more attention. Whether it is China or Intel, Samsung, Qualcomm and other giants, RISC-V is also regarded as a potential alternative for ARM and even x86.”In fact, NVIDIA is also very concerned about the RISC-V architecture. It has joined the RISC-V Foundation early and has done a lot of research. Recently, it has also revealed the possibility…

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EE Times Article: X-FAB And Efabless Deliver Open Source Mixed-Signal SoC

Mixed signal foundry X-FAB Silicon Foundries and crowd-sourcing IC platform Efabless Corp. have announced silicon availability of a RISC-V based mixed signal system-on-chip (SoC) reference design. The open-source semiconductor project went from design start to tape-out in less than three months using the Efabless design flow based on open-source tools.The mixed-signal SoC, called Raven, is based on the community developed ultra-low power PicoRV32 RISC-V core.  Efabless has successfully bench-tested the…

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Phoronix Article: The State Of RISC-V For Debian 10 “Buster”

Debian’s RISC-V support has been coming together but how’s the state of affairs for the imminent Debian 10.0 “Buster” release?The RISC-V 64-bit port of Debian GNU/Linux has been building more than 80 percent of the massive Debian package-set. Or if accounting for architecture dependent packages, the RISC-V port is seeing around 90 percent of packages building.The main blockers in the RISC-V ecosystem from getting the remaining Debian packages built and allowing…

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EETimes On Air: Risking RISC-V, Engineers & The Gig Economy, Chiplets

BRIAN SANTO: I’m Brian Santo, EE Times Editor in Chief, and you’re listening to EETimes on Air. This is your briefing for the week ending June 14th.Today we’ll be talking about… RISC-V, a free and open processor architecture. We examine the potentially profound consequences RISC-V might have for the smartphone market… We’ll also be talking about engineering education. We’ve heard about the need for STEM education, but the required skillset…

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EE Times Article: RISC-V Moving Beyond Academia, New Group Offers Hardened SoCs

Over the last year or so, we’ve heard many times that ‘this is the moment for RISC-V.’ This week, I attended the RISC-V workshop in Zurich to get an idea of where it really is at right now. The conclusion: while there is still a lot of background work to be done for RISC-V to go mainstream, the signs are that all the triggers to make it happen are now…

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CNX Software Article: Perf-V Is Another FPGA Based RISC-V Development Board

There are already some RISC-V development boards with silicon featuring RISC-V instruction set such as SiFive’s HiFive1 or Kendryte KD233 board.  But beauty of RISC-V is that you can customize the instructions set, and if that’s your goal, an FPGA board provides the flexibility you need.While in theory you could use pretty much any FPGA board with enough logic elements, it may help to get started with boards that are designed for this…

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