The RISC-V ISA has been trying to provide an open source alternative to Intel and AMD processors based on the x86 / x86-64 architecture. In addition to being open source and development free of royalties, its developers want to make these chips the safest microprocessors in the world.To do this, they are working in an open source hardware enclave. This type of component has become famous in Apple chips that keep our…

Semiconductor Engineering’s Ed Sperling has published extracts of a round-table with Rambus’ Helena Handschuh, Microsemi’s Richard Newell, and Galois’ Joseph Kiniry on the impact the open RISC-V instruction set architecture (ISA) can have on security.“With open source, you have the opportunity to review it and come up with comments, feed it back to the community, and as a group you can advance maybe not faster but better,” explains Handschuh. “You…

Bluespec, Inc. releases a second family of open-source RISC-V processors to spur open innovation: New Flute RISC-V processor is easily customized for IoT RISC-V is ushering in a new era of processor innovation Download a 32-bit or 64-it RISC-V core (here) December 13, 2018 – Bluespec Inc. has released Flute, its second in a family of commercially supported open-source RISC-V processors. Flute is a configurable 5-stage application processor complementing the…

OpenISA has officially launched the VEGAboard microcontroller development board, based on the PULP Platform’s RI5CY and Zero-RI5CY RISC-V core, and it’s giving them away to encourage adoption of the free instruction set architecture (ISA).Developed in partnership with the Parallel Ultra Low Power (PULP) Platform, Express Logic, Foundries.io, Ashling, IAR Systems, and Segger, the OpenISA VEGAboard is powered by an NXP Semiconductors RV32M1 chip which combines Arm Cortex-M0 and Cortex-M4 CPUs…

Not only are more companies accepting and adopting RISC-V, more governments are adopting it. India has already used RISC-V as a national ISA transaction, DARPA in the United States requires RISC in the security collection proposal and Israel is also building a RISC-V based incubator. You have freedom when you choose RISC-V.Directed by the Ministry of Industry and Information Technology, Shanghai Municipal People’s Government, China Semiconductor Industry Association, China Electronic Information…

The Berkeley Out-of-Order Machine (BOOM) is an open source RV64G RISC-V core written in the Chisel hardware construction language, and mainly ASIC optimized. However, it is also usable on FPGAs, and developers support the FireSim flow to run BOOM at over 90 MHz on Xilinx Ultrascale+ FPGAs found in Amazon EC2 F1 instances.The BOOM core was created at the University of California, Berkeley in the Berkeley Architecture Research group, in order to create a…

Processors and FPGAs go together like chocolate and peanut butter, but it took a few years to get the recipe just right. Early turn-of-the-millennium attempts included the Xilinx Virtex II Pro with an on-chip PowerPC processor core and Altera’s Excalibur device with an ARM922T processor core. These early products are considered market failures. Actually, Kevin Morris called the Altera Excalibur “a monumental flop” in his article titled “Shaking Up Embedded…

The greatest hardware hacks of all time were simply the result of finding software keys in memory. The AACS encryption debacle — the 09 F9 key that allowed us to decrypt HD DVDs — was the result of encryption keys just sitting in main memory, where it could be read by any other program. DeCSS, the hack that gave us all access to DVDs was again the result of encryption keys…

Semiconductor Engineering sat down with Helena Handschuh, a Rambus fellow; Richard Newell, senior principal product architect at Microsemi, a Microchip Company; and Joseph Kiniry, principal scientist at Galois. What follows are excerpts of that conversation.Semiconductor Engineering: There has been a lot of discussion about the security advantages of RISC-V because there isn’t speculative execution or branch prediction, which were used in other proprietary designs to speed them up. Is that true?Richard Newell:…

So it was at last week’s RISC-V Summit, a four-day love-fest in the city named for Saint Clare in her eponymous California Valley of Heart’s Delight. What all the exhibitors and speakers had in common was a deep financial commitment to the somewhat new RISC-V processor architecture. Apart from that, however, their opinions, their motivations, and their convictions were all over the map.RISC-V, of course, is “that Berkeley academic project,” a free and open-source…