SEGGER continues to strengthen its position in relation to the RISC-V instruction set architecture. The company’s products are already fully compatible with SiFive’s RISC-V processor cores, and now its J-Link probes deliver support for the new SiFive Insight debug/trace solution. This includes SiFive’s latest Nexus-based trace implementation, which enables ongoing monitoring and recording of processor instruction execution. article: https://www.segger.com/news/segger-announces-comprehensive-support-for-sifive-insight-debugtrace-platform/

Week In Review: Design, Low Power

The Nucleus real-time operating system is already in use in over 3 billion devices. Now Mentor has given the RTOS a few important innovations.With its GAP9, Greenwaves in turn has developed an IoT application processor that, compared to GAP8, achieves higher performance with less power consumption.article: https://www.elektroniknet.de/markt-technik/embedded/rtos-und-risc-v-prozessor-174721.html

The commercial market for RISC-V has established a firm foothold in embedded processing. The open-source RISC-V instruction set architecture has been a hot topic for the past couple of years and continued to be a couple of weeks ago in Embedded World as highlighted in our VDC View covering the event. The ecosystem continues to expand led by the RISC-V Foundation and add leading hardware, software and cloud technology providers to its…