CODASIP TEAMS UP WITH WESTERN DIGITAL TO SUPPORT ADOPTION OF OPEN-SOURCE PROCESSORS

Munich, Germany – December 10th, 2019 – Codasip GmbH, the leading supplier of configurable RISC-V® embedded processor IP, announced today that it has joined forces with Western Digital Corp. (NASDAQ: WDC) to become the preferred provider of hardware implementation packages and expert technical support for users of Western Digital’s SweRV CoreTM EH1, a RISC-V core currently available to the open-source community and further supported by the open-source development organization CHIPS…

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RISC-V Foundation Seeks Technology Leader

The RISC-V Foundation is looking for a technology leader who can foster a successful technical ecosystem with deep member and community engagement and meaningful progress across technical imperatives in growing adoption of the RISC-V architecture. The technology leader will facilitate the technical vision, cultivate stakeholder engagement, and drive the strategy in collaboration with RISC-V members. This person will be the Foundation’s technical leader in facilitating progress across our workgroups and…

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Tensorflow Lite in Zephyr on LiteX/VexRiscv

While much of the focus for the recent developments in AI has been on cloud-centric implementations, there are many use cases where AI algorithms have to be run on small and resource constrained devices. Google’s TensorFlow Lite, a smaller brother of one of the world’s most popular Machine Learning frameworks, is focused on exactly that – running neural network inference on resource constrained devices. A more recent but very exciting…

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Andes certifies Imperas models and simulator as reference for new Andes RISC-V Vectors Core with lead customers and partners  

Imperas code morphing simulation technology, virtual platforms and tools used by lead customers for early software development and high-level architectural explorationOxford, United Kingdom, December 4th, 2019 — Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced with Andes Technology Corporation, the close collaboration with lead customers for the latest Andes Vectors Core NX27V, which addresses the requirement for advanced ML (machine learning) and AI (artificial…

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RISC-V Foundation Founding Member Andes Technology Turns Platinum

Hsinchu Taiwan, Dec. 03, 2019 (GLOBE NEWSWIRE) — Andes Technology Corporation (TWSE: 6533), a founding member of the RISC-V Foundation and the leading supplier of 32/64-bit embedded CPU cores with solutions serving in excess of 1-billion diversified SoCs yearly, today announced that it has upgraded its membership in the RISC-V Foundation to Platinum.Andes Technology joined the RISC-V Foundation in 2016 as a founding member and brought its extensive experience in…

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A RISC-V Fully European Platform For Space | Julien Happich, eeNews Europe

Officially launched in October, the Horizon 2020 European project De-RISC (Dependable Real-time Infrastructure for Safety-critical Computer) has gathered an international consortium to develop a hardware and software platform based around the RISC-V ISA for the space and aviation market. article: https://www.eenewseurope.com/news/risc-v-fully-european-platform-space

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IAR Systems Updates RISC-V Development Tools With Support For RV32E And Atomic Operations

Uppsala, Sweden—December 3, 2019—IAR Systems®, the future-proof supplier of software tools and services for embedded development, announces that a new version of the toolchain IAR Embedded Workbench® for RISC-V is now available. Version 1.20 adds support for the base instruction set RV32E and also the standard extension for Atomic operations (A).One of the major benefits of using RISC-V is the flexibility the architecture provides, which enables OEMs as well as…

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Think Silicon® Demonstrates Early Preview Of Industry’s First RISC-V ISA Based 3D GPU At The RISC-V Summit

San Jose, California / Athens , Greece – Dec. 2nd, 2019 – Think Silicon, recognized for the successful ultra-low power NEMA® GPU-Series for MCU driven SoCs, announced the demonstration of the industry’s first RISC-V ISA based 3D GPU — the NEOX|V™. Attendees at the RISC-V Summit, in San Jose, California, will have the first opportunity to witness this new GPU innovation designed for the rapid deployment of Computer Graphics, Machine Learning…

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NEOX V Announced By Think Silicon As First RISC-V 3D GPU | Michael Larabel, Phoronix

While there has been the Libre RISC-V community-driven effort to create a RISC-V graphics processor that basically amounts to a RISC-V core with vector extensions/improvements and running a Vulkan software implementation (though they are now reportedly eyeing POWER instead of RISC-V), Think Silicon has announced the first actual RISC-V ISA based 3D graphics processor.article: https://www.phoronix.com/scan.php?page=news_item&px=NEOX-V-RISC-V-3D-GPU

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