RISC-V Community News Collection: November 22, 2019

The RISC-V community has exploded over the past year, creating a great deal of news. We will continue to post important news as it appears, with occasional group posts like this one that collect news from a variety of sources all in one place.

Andes Core and Secure-IC Strategic Alliance
By Andes Technology, EET Taiwan
Nov. 20, 2019
Coverage

First European Pre-Exascale Supercomputers Forgo Homegrown CPUs
By Michael Feldman, The Next Platform
Nov. 20, 2019
Coverage

Running the RISC-V Processor on Arty A7
By Digilent Inc., TechWorld
Nov. 20, 2019
Coverage

Widora Teases Compact Kendryte K210-Powered Binocular Facial Recognition Board
By Emmanuel Odunlade, Electronics Lab
Nov. 19, 2019
Coverage

RISC-V Not So Risky
By William G. Wong, ElectronicDesign
Nov. 19, 2019
Coverage

Emulating RISC-V on an FPGA
By Gerrit Coetzee, Hackaday
Nov. 19, 2019
Coverage

RIOS: Rooted in Tsinghua-Berkeley Shenzhen College, Spawned RISC-V Open Source Ecological Development
By Gu Zheng, EET China
Nov. 18, 2019
Coverage

RISC-V Markets, Security And Growth Prospects
By Ed Sperling, Semiconductor Engineering
Nov. 18, 2019
Coverage

ArchiTek Select SiFive and DTS-Insight To Enable Next-Generation AI Solution Development
By SiFive, PRNewswire (Press Release)
Nov. 18, 2019
Coverage

Secure-IC and Andes Technology Jointly Provide Cybersecurity Enhanced RISC-V Cores
By staff, Andes Technology (Press Release)
Nov. 13, 2019
Coverage

Aerendir Mobile Integrates SiFive’s Processor Core IP for Edge AI
By Luana Pascu, Biometric Update
Nov. 13, 2019
Coverage

Jingxin Technology and Secure-IC Alliance Provide RISC-V Core for Network Security
By staff, CTIMES (Chinese)
Nov. 13, 2019
Coverage

The European Laboratory for Open Computer Architecture Will Be Based in Barcelona
By staff, IT User (Spanish)
Nov. 13, 2019
Coverage

UET Hosts SiFive Tech Symposiums Pakistan 2019
By Daniyal Sohail, UrduPoint
Nov. 13, 2019
Coverage

Google’s OpenTitan Chip Could Make Data Centers More Secure… Someday
By Maria Korolov, Data Center Knowledge
Nov. 12, 2019
Coverage

Aerendir and SiFive Team Up to Make On-Device AI More Affordable
By Eric Weiss, FindBiometrics
Nov. 12, 2019
Coverage

RISC-V: Why The ISA Battles Aren’t Over Yet
By Maya Posch, Hackaday
Nov. 12, 2019
Coverage

Aerendir Mobile Inc. and SiFive Inc. Collaborate to Accelerate the Adoption of AI-Enabled Processors
By SiFive, PRNewswire (Press Release)
Nov. 12, 2019
Coverage

MIT Develops RISC-V Microprocessor Based on Carbon Nanotube FET
By Nitin Dahad, EE Times Taiwan
Nov. 11, 2019
Coverage

Observer Simplifies Multi-Sensor Aggregation on FPGAs — By Giving Each Its Own RISC-V CPU
By Gareth Halfacree, Hackster.io
Nov. 11, 2019
Coverage

New LOCA Facility to Develop Open Computer Architectures at BSC in Barcelona
By staff, insideHPC
Nov. 11, 2019
Coverage

Using RISC-V in FPGAs for Strategic Defense Systems
By Ted Marena, Military Embedded Systems
Nov. 10, 2019
Coverage

Embecosm’s Mary Bennett Wins TechWorks UKESF Scholar of the Year Award
By Sarah Cook, Embecosm (Blog Post)
Nov. 7, 2019
Coverage

Fraunhofer Secure’s Local AI Processing for Sensors
By Steve Bush, Electronics Weekly
Nov. 6, 2019
Coverage

Open Titan: Google Launches Open Source Project for Secure Root of Trust
Sebastian Gerstl, Elektronik Praxis (German)
Nov. 6, 2019
Coverage

Supercon Keynote: DR. Megan Wachs on RISC-V
By Elliot Williams, Hackaday
Nov. 6, 2019
Coverage

IAR Systems Opens Office in Taiwan
By staff, IAR Systems (Press Release)
Nov. 6, 2019
Coverage

GlobalFoundries and SiFive to Design HBM2E Implementation on 12LP/12LP+
By Anton Shilov, AnandTech
Nov. 5, 2019
Coverage

A Guide to Choosing the Right IoT Processor for Your Company
By Crystal Bedell, IoT World Today
Nov. 5, 2019
Coverage

UltraSoC Links with Europractice
By David Manners, Electronics Weekly
Nov. 5, 2019
Coverage

OpenTitan: Google Reveals Security Chip with RISC-V Technology
By Christof Windeck, Heise (German)
Nov. 5, 2019
Coverage

Cambridge Boffins and Google Unveil Open-Source OpenTitan Chip: Because You Never Know Who You Can Trust
By Tim Anderson, The Register
Nov. 5, 2019
Coverage

Gigantic FPGA in a Game Boy Form Factor, 2019 Supercon Badge is a Hardware Siren Song
By Mike Szczys, Hackaday
Nov. 4, 2019
Coverage

OneSpin CEO Gives Visionary Talk and Insights on the Challenges Facing Design and Verification with the Onset of Artificial Intelligence and the RISC-V Era
By staff, OneSpin Solutions (Press Release)
Nov. 4, 2019
Coverage

UltraSoC Furthers Academic Support with Europractice Partnership
by David Marsden, UltraSoC  (Press Release)
Nov. 4, 2019
Coverage

SiFive Introduce First RISC-V OoO CPU Core : U8-Series Processor IP
By Julian Horsey, Geeky Gadgets
Nov. 1, 2019
Coverage

China Vigorously Develops RISC-V Architecture Processor
By staff, cnBeta (Chinese)
Oct. 31, 2019
Coverage

 SiFive Announces First Out-of-Order RISC-V CPU, Boosts Efficiency, Performance
By staff, ExtremeTech
Oct. 31, 2019
Coverage

SiFive Readies U8-Series RISC-V Core Designs To Compete With ARM’s Cortex-A72 Models
By Bogdan Solca, Notebookcheck
Oct. 31, 2019
Coverage

Porting Apache Mynewt OS to GigaDevice GD32 VF103 on RISC-V
By Lup Yuen Lee, Medium
Oct. 29, 2019
Coverage

Open-Source Chips To Help Growth Of Digital Society
By Fan Feifei, China Daily
Oct. 22, 2019
Coverage

F# Implementation Of The RISC-V Instruction Set Architecture Specification
By staff, cnBeta (Chinese)
Oct. 22, 2019
Coverage

RISC-V Architecture MCU Platform Open Source, AIoT Era Will Become A Chip Customization Era
By staff, EET China (Chinese)
Oct. 22, 2019
Coverage

New Wio Lite RISC-V WiFi Board With ESP8266 Module For WiFi Connectivity Launches For $6.9
By Emmanuel Odunlade, Electronics Lab
Oct. 20, 2019
Coverage

The Open Source CPU RISC-V
By Tam Hanna, Heise (German)
Oct. 20, 2019
Coverage

FOSDEM 2020 RISC-V Devroom Opens Call For Participation
By Gareth Halfacree, AB Open
Oct. 18, 2019
Coverage

Is NVIDIA Doubling Down On RISC-V?
By SYNCED
Oct. 10, 2019
Coverage

Rambus’ Ben Levine Talks IoT Security And Cryptography With EDA Café
By Rambus (Blog Post)
Oct. 9, 2019
Coverage

RISC-V: Fraunhofer IMS Introduces Microcontroller Core
By staff, All Electronics
Oct. 8, 2019
Coverage

The Zephyr Project Welcomes Eclipse IoT And Oticon As Members To Create A Safe And Secure RTOS
By Zephry (Press Release)
Oct. 8, 2019
Coverage

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