Aldec @ DAC 2020: Presenting RISC-V Verification Methodologies and Solutions

Henderson, NV – July 15, 2020  – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and SoC designs, is presenting RISC-V Verification Methodologies and Solutions at the 2020 Virtual Design Automation Conference (DAC) on July 20-24, 2020.

Article: https://www.aldec.com/en/company/news/2020-07-15/444

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