Membership Representative to the Board: 2022 Election

Yungang Bao

Deputy Director, ICT-CAS

Biography:

Yungang Bao is a professor of Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) and the deputy director of ICT, CAS. Prof. Bao founded China RSIC-V Alliance (CRVA) and serves as the secretary-general of CRVA. His research interests include computer architecture and computer systems. He is leading the XiangShan project (https://github.com/OpenXiangShan/XiangShan
), which aims to build an open-source high performance RISC-V core. He launched the One Student One Chip (OSOC) Initiative in 2019, which trains undergraduates to build real chips and has already attracted about 1800 participants from 200+ universities. His prior research works such as Labeled von Neumann Architecture (LvNA), Hybrid Memory Trace Tool (HMTT), Partition-Based DMA Cache and PARSEC 3.0 have been adopted by the industry including Alibaba, Huawei, Intel, Microsoft and also published on top conferences and journals such as ASPLOS, Communication of the ACM, HPCA, ISCA, NSDI and SIGCOMM etc. He was invited to present plenary keynote speeches at China National Computer Congress (CNCC) in 2016 and at ARM Research Summit 2018. He was the winner of CCF-Intel Young Faculty Award of the year for 2013 and the winner of CCF-IEEE CS Young Computer Scientist Award and China’s National Lofty Honor for Youth under 40 of the year for 2019.

Comments on why I want to be on the RISC-V Board of Directors:

I will make the following contributions if I serve as a BoD:

1) Following the philosophy of Linux, I will unite more and more companies and organizations to keep developing an open-source high performance RISC-V CPU core (i.e., XiangShan), which is open and free to the global RISC-V community. I believe that XiangShan will be a good platform for building POC for many specification of RISC-V International.

2) More and more Chinese companies become enthusiastic to RISC-V, but still face many obstacles to contribute more to the whole community. As the secretary-general of China RISC-V Alliance (CRVA), I have connections with hundreds of companies and will help them engage in the activities of RISC-V International.

3) The One Student One Chip (OSOC) Initiative will train thousands of talent architects with good engineering skills in the next five years. I will encourage them to participate in the RISC-V community and make contributions to the RISC-V ecosystem. They will form a talent pool for companies.

Shreyas Derashri

Vice President of Compute, Imagination Technologies

Biography:

Shreyas is Vice President of Compute at Imagination, responsible for Imagination’s RISC-V CPUs, AI and Heterogeneous compute products and solutions.

He has spent over 20 years in the semiconductor industry both at start-ups and large corporations. He started his journey in the UK designing CPUs at Arm and moved to a start-up, Apical, where he was a core catalyst in its successful journey from an early start up stage through to its acquisition. At Apical his roles included Head of Engineering and Head of Strategic Marketing. Apical was acquired by Arm.

At Arm Shreyas was responsible for product management for Arm’s Imaging and AI products and guided those technologies into billions of devices.

He joined Imagination in 2019 to work on business development and then moved into a product leadership and strategy role. He has been at the heart of Imagination’s RISC-V strategy.

Shreyas holds an MBA from University of Cambridge – Judge Business School, Masters in Analogue and Digital IC Design from Imperial College London, graduating top of his class with distinction. Shreyas is also the recipient of Bhamashah award (India) with double gold medal for his B.Eng. in Electronics and Communications.

Comments on why I want to be on the RISC-V Board of Directors:

I passionately believe that what we do now will be instrumental not only to the level of RISC-V’s success but also the character of that success. Now is the time to double-down on RISC-V’s partnerships-based success model to create a strong ecosystem that does not simply rival those of other processors but exceeds them. Imagination is probably the most prominent IP company to back RISC-V but we do so with a complete commitment to the community and it is very important to me, and Imagination, to be giving back to the RISC-V International so that we can accelerate a heterogeneous future with RISC-V, minimize fragmentation, and define a clear and credible strategy to become the leading global processor standard.

Renu Raman

Chief Technologist, VMware

Biography:

Renu Raman is Chief Technologist with VMware in their office of the CTO (OCTO), which is leads the industry in cloud and virtualization platforms. At VMware, he leads and works on a number of initiatives where next generation applications and hardware intersect and making sense of what that means to the core products and services at VMware. Currently he is involved in driving multiple initiatives including next generation memory, accelerators for new workloads, transform the operating model from ITops to SRE within the VMware eco-system and a new initiative on hybrid cloud computing in partnership with Intel, Equinix and key ISVs for at scale Private cloud. Prior to VMware, Renu was Vice President in SAP’s cloud architecture and engineering group responsible for computing and storage platforms. At SAP, he has a dual role of both architecting and managing the development and delivery of SAP’s compute and storage infrastructure.

Prior to SAP, he founded Unity Microsystems, which was focused on leveraging flash and new memory technology to build rack scale memory computing. That work led him to SAP. Prior to Unity, he was an executive in residence at Tallwood Venture Capital – a leading semiconductor focused venture firm. He was a board observer in multiple companies (Alphion, Pixim, Audience, Astute, Ikanos). Prior to Tallwood, Renu was VP/GM at InSilica where he initiated and led the development of industry’s lowest cost, lowest power cameras for cellular applications which was sold to Aptina.

Renu’s professional career started at Sun Microsystems spanning more than a decade. At Sun, Renu was responsible for delivery of eight generations of SPARC microprocessors starting with ECL based SPARC in the early years of RISC evolution to advanced multi-core SPARC. Starting with Industry’s first highly integrated CMOS microprocessor (microSPARC) in the 1991, he led the transition to CMOS and developed CAD methodologies that was the basis for Sun’s microprocessor development throughout the 1990s. In the late 1990s recognizing the diminishing return from Clock rate growth in microprocessor performance, he led the initial development of multicore and multithreaded processor architectures within Sun that evolved into the industry leading Niagara family of designs. Renu brings a diverse background ranging from computer system architecture, semiconductors (processors) , Storage, networking and Computer aided design (CAD) and now cloud infrastructure and virtualization.

Comments on why I want to be on the RISC-V Board of Directors:

1) I had the fortune to have led SPARC through the 1990s in both implementation and its industry impact including doing version of SPARC to be open sourced (microSPARC and UltraSPARC T2). , Lots of lessons learnt and I see RISC-V doing a much better job in enabling true open source hardware and potentially having a much bigger impact to the industry at large. Like Opensource enabled the public cloud to build and scale their cloud, opensource hardware is going to enable the next wave of ML enhanced processing elements of all kinds and forms. I hope to both participate, shape, learn and join forces with the industry veterans to have a big impact.
2) VMware is looking at RISC-V from an infrastructure processor perspective and exepcting RISC-V to join ARM in variety of computing devices (IoT). We would like to join the community to help shape its long term roadmap, architecture as it relates to hypervisors, device infrastructure consistency and ISA extensions for accelerating new workloads and create new components for the emerging decentralized and heterogenous computing era.
3) Raise awareness to the VMware community (internal to the company as well as broader vSphere community ) at large to adopt RISC-V and provide a vibrant and rich eco-system of vendors to enhance the platform.
4) Network and meet with other industry experts to help grow the overall footprint and pie of computing (RISC-V inclusive) in a cohesive and architecturally elegant and simple form.

Philipp Tomsich

Chief Technologist & Founder, VRULL GmbH

Biography:

Dr. Philipp Tomsich is the Chief Technologist and Founder of VRULL, an engineering consultancy focused on building, enabling, and optimizing the software ecosystems for next-generation silicon solutions.

Philipp brings broad experience and expertise in runtime systems (including Java VMs, compilers, operating systems kernels, and static code analysis), high-assurance applications, secure/trusted boot, and embedded hardware. His earlier contributions to open-source compilers have been centered on ARMv8 and, more recently, on RISC-V. He has worked on languages and compilers for multi-core systems for over twenty years, and led multiple engineering projects for high-assurance government applications.

Philipp started his career as a compiler engineer at Silicon Graphics Inc., worked several years as a consultant in banking and government IT and has held in his early years teaching and research roles at the Vienna University of Technology, where he also graduated with a degree and a doctorate in Computer Science. In Austria, Philipp is a court-certified expert on embedded systems, low-level programming, programming languages, compilers, and software performance.

Prior to founding VRULL, Philipp founded and bootstrapped Theobroma Systems (a Software and Hardware engineering company offering tailored & standard modular solutions for high-assurance computing, acquired later by Cherry GmbH). At VRULL, he today manages engineering teams working on the GNU toolchains, LLVM, QEMU, Apache TVM, the Linux kernel, cryptographic libraries, and Embedded Rust.

Philipp today supports the RISC-V mission as the Chair of the Applications & Tools (formerly: “Software”) Horizontal Committee and as the Acting Chair of the Privileged Software Horizontal Committee. In these roles, he oversees the software ecosystem outreach, standardization of Platforms, and the development of performance modeling, dynamic instrumentation, and analysis tools for RISC-V. His contributions to RISC-V have been recognized with both the 2021 RISC-V Board of Directors Technical Leadership Award and the 2021 RISC Community Contributor Award.

Comments on why I want to be on the RISC-V Board of Directors:

Since joining the RISC-V two years ago, I had a first-row seat to both the evolution of our ISA and the efforts to further build our software ecosystem. This allowed me to understand some of the unique challenges and opportunities in our mission:

• Complex interactions and a closed feedback-loop exist between new ISA extensions and software enablement: our software drives the quantitative measurements and prototypical software may bias the design decisions. Our software ecosystem needs to be closely involved early in the development of new ISA extensions to ensure that the extension development is effective and can later be adopted by production software.
• Innovation begets fragmentation: to enable our members to innovate, we must embrace fragmentation and evolve the software ecosystem towards dynamic detection of features and the efficient support for optimised functionality.

As a member of the RISC-V board of directors, I will continue to drive the empowerment of the software ecosystem perspective within RISC-V and work towards making RISC-V the premier platform for software innovation. To me, success is measured by seeing software, workloads, ISV applications and novel development tools innovate “first on RISC-V” and deliver an optimized end-to-end experience (from hardware to software) to users.

Oliver Kong

Chief Expert, ZTE

Biography:

Oliver is the Chief IC expert of Sanechips, a subsidiary of ZTE coporation, the 2nd fabless IC design house in China.
He is responsible for leading CPU core develop team and HPC product line.
Oliver has 20+ years experience on CPU micro-architect design and ISA design.
Oliver was a mobile CPU architect in Hisilicon and leading mobile heterogenous computing technology.
Oliver was a senior CPU architecutre in MIPS/Wave Computing and has 10+ years experence on MIPS ISA design, including MIPS Virturlizaiton, MIPS R6, MIPS SMID Architecture, Crypto, nanoMIPS…etc.

Comments on why I want to be on the RISC-V Board of Directors:

Help RISCV to grow quickly, improve ISA completeness, promote ecosystem

Karel Masařík

President and Founder, Codasip GmbH

Biography:

Dr Karel Masařík undertook research in the use of processor architecture description languages and design automation tool at Brno University of Technology. This included research into hardware/software co-design as well as formal and functional verification of processor designs. He achieved a Ph.D. in Computer Science in 2008. He led the development of Codasip’s underlying technologies as part of the technological incubator and then founded Codasip private company in 2014. Codasip launched its processor development toolset, Codasip Studio, in 2014 and announced its first RISC-V processor core in late 2015. As Codasip’s CEO, Dr Masařík has led the company through its seed funding round in 2014 also consequent founding rounds till end 2021 and has overseen Codasip international expansion. From the end of 2021, Dr Masařík is acting as President responsible for the advanced research in the areas as security, automotive, cloud-based EDA, university programs, graphics and AI/ML.

Comments on why I want to be on the RISC-V Board of Directors:

Codasip is closely working with universities on mass adoption of new style of the microprocessor design relaying on highly automated approach instead of traditional manual one, where the goal is to create an Open Architecture Description Language which will allow to unify several EDA vendors and to achieve one homogeneous design flow from SoC up to microprocessors. After achieving this goal, the ambition is to start the standardisation process (e.g., IEEE) of Open Architecture Description Language similarly to Verilog RTL language standardisation process.

Since RISC-V is an open standard which can be implemented by anybody;harmonizing all the EDA tools for SoC and processor design will provide highly productive environment which will allow fast innovation in the semiconductor industry, especially moving the EDA to the cloud. This step will decrease the barrier for the mass adoption, will allow much flexible SaaS business model more convenient for SME, academia and research institutions, and RISC-V community. At the same time, the EDA in the cloud will enable sharing workspaces with commercial grade RISC-V IP for research and educational purposes and will allow fast cross-border and institutional cooperation on specific projects, e.g., security, AI, and automotive. I strongly believe that by democratising the access to EDA and processor RISC-V IP in the underlined way, the semiconductor segment will reach a very efficient and fast innovation cycle. As the board member I will initiate and coordinate this highly strategic initiative.

Frans Sijstermans

Vice President of Hardware Engineering, NVIDIA

Biography:

Frans Sijstermans earned his MSc degree in Computer Science from the Eindhoven University of Technology in 1985. He worked as a researcher at Philips in The Netherlands and Palo Alto, USA, until 1998. After that he held various managerial positions at Philips Semiconductors, TriMedia, and Equator. He joined NVIDIA in 2004, where he is responsible for all RISC-V processors, security IP, video codecs, camera & display controllers, vision & DL accelerators, and GSYNC products. He has been active in the open source community as a member of the inaugural board of the RISC-V foundation and the Alliance for Open Media. Also, his team open sourced NVDLA, NVIDIA’s inferencing accelerator.

Comments on why I want to be on the RISC-V Board of Directors:

Processor architectures have been a theme throughout my career: multi-processor systems during my research years at Philips, VLIW at TriMedia and Equator, and micro-controllers, security processors, and Vision DSPs at NVIDIA. Also, open source has always fascinated me as it creates a win-win situation where everybody benefits, in stark contrast to the zero-sum game that we usually play in our competitive industry. Becoming a member of the inaugural board of RISC-V was thus an easy decision;I wanted to be a part of this exciting new development. It saddened me when NVIDIA’s attempted ARM acquisition created a possible conflict of interest. With that obstacle gone, I would love to get another chance to contribute as a board member.

Besides my personal interest, there is also a clear NVIDIA interest. All NVIDIA chips contain multiple RISC-V cores. My team has been working on an ever larger set of cores, including both 32-bit and 64-bit cores, secure and safe cores, multi-issue cores, multi-processor implementations, and vector processors. We are thus a big consumer of RISC-V technology and the future of RISC-V is important to us. We contribute to missing specifications, e.g. in the memory model, virtual memory, secure cores, and IO PMP work groups. Even when we are contributing to the specs, we get the advantage of in-depth review by the best experts in academia and the industry. From my perspective, the description of open source as “give a penny, take a penny” therefore somewhat misses the mark; rather it is “take a penny by using an open spec, take another penny by contributing to an open spec” (and the stack of pennies magically grows by doing this!).

I see software availability as the major challenge for RISC-V in the coming years. I believe that it is critical that we create solutions for specific applications or markets. Security has been one of the early focusses for the foundation and it is a good example of an application where RISC-V has been adopted as the core of most modern security processors. We can create similar success stories for other fields by swarming the application. This is one of the areas, I would like to contribute to if elected to the board.

Cosimo Damiano Gianfreda

Chief Executive Officer, E4 Computer Engineering Spa

Biography:

As strongly enthusiastic about IT and as one of the founders of the 20-years old E4 Computer Engineering company, Cosimo has actively contributed in the creation of a company that from an hardware integrator is now a solution manufacturer and a service provider internationally renowned for the high-level expertise of its engineers in the field of High Performance Computing, High Performance Data Analytics, AI, Deep Learning and Cognitive Computing.
Cosimo loves scouting and testing new technologies, which means he is often travelling to source the best and most advanced companies to partner with, and get access to the latest technologies to bring inside the company.
As E4 grew in revenue and staff, he hand-picked some of the best engineers to collaborate with, with the aim to create a diverse team that is at the forefront of innovation.

Comments on why I want to be on the RISC-V Board of Directors:

E4 joined RISC-V international recently, and I may not yet be known to most of the members. I’ve participated to the RISC-V Spring week in Paris and by direct contact or via participating to the webinars and other online sessions I’m coming to know a larger and larger number of members. A few words about me and why I’m applying for the role of Representative for Community Organization Members: designing and testing platforms and infrastructures for HPC users describe in a nutshell my career. I have designed the first ARM-based cluster, not only building a platform, but creating a community of users, interested people, developers, thinkers around it. In Paris and in the webinars I feel in the RISC-V community the excitement I was looking for and I want to be part and drive this excitements to achieve new development.

Charlie Hauck

CEO, Bluespec, Inc.

Biography:

Charlie Hauck is CEO of Bluespec, Inc., a company focused exclusively on RISC-V IP and tools and a founding member of RISC-V International. Charlie has over 30 years of experience with processors for ASIC, IP, and EDA, and has held senior positions at Kendall Square Research, LSI Logic, Lexra, and Faraday Technology. Under his direction, Bluespec has made significant contributions to the RISC-V ecosystem in formal modeling, libraries, platforms, Linux kernel, open-source processors, and the BSV high-level HDL (used to implement some notable RISC-V cores). Charlie has 15 years of startup business experience and is currently the Treasurer for RISC-V International. He has a BSEE from Johns Hopkins University and an MSEE from MIT.

Comments on why I want to be on the RISC-V Board of Directors:

About four years ago over a series of RISC-V BoD meetings, it became clear that an ISA formal spec was high on the list of priorities.This led to Bluespec’s CTO heading a task group that produced the ISA formal spec that was eventually ratified, a contribution for which he received the “RISC-V Foundation Board of Directors Award”.

My motivation for wanting to be on the RISC-V BoD is to participate in discussions on BoD priorities to identify similarly important ways that Bluespec can contribute.

Today, the RISC-V software ecosystem is the BoD’s highest priority. Bluespec is again well-positioned to contribute, with an executable modeling technology that can quickly track RISC-V platform and profile specs and eliminate the heavy dependence on physical development boards. My reelection to the RISC-V BoD would enable me to optimally align Bluespec’s priorities with the challenges facing the RISC-V software ecosystem.

Bernard Xiong

Founder, RT-Thread

Biography:

Bernard Xiong, the creator and originator of RT-Thread, has more than 20 years of experience in embedded systems and wireless communication. Bernard Xiong created RT-Thread Open Source Operating System in 2006 in a form of Open Source Community Powered. He gathered the top engineers and open-source advocates to join the project, and on the system side, he put forwarded and applied the real-time object-oriented design, to make the RT-Thread autonomous Operating System kernel and Micro-Kernel Operating System RT-Thread Smart stand out, as well as developed a large number of mature and stable software components, such as file system, PersimUI, and many others.

Comments on why I want to be on the RISC-V Board of Directors:

RT-Thread has worked a lot to promote RISC-V in China and worldwide
1) RT-Thread has supported RV32, RV 64, RISC-V Soft Cores. Ported many of RISC-V based dev boards with open source RT-Thread RTOS.
2) RT-Thread Studio IDE tool to support RISC-V so many embedded developers can easily get started with RISC-V development.
3) Successfully created RISC-V MCU Design Challenges that gained over 500 applications.
4) Launched crowdfunding on Crowd Supply for the RISC-V Based Dev Boards and more RISC-V dev boards are on the way!
5) Joined the RISC-V Mentorship Program and looking to get another RISC-V-based dev board to get to mass production.
6) Successfully hold the 2022 RT-Thread Global Tech Conference from June 1- June 3 with 29 topics featured, worth mentioning that there are 4 topics focused on RISC-V.

We want to contribute more to RISC-V by joining the RISC-V Board of Directors.

Liu Ben

Senior Article Editor, International Journal of Law, Ethics, and Technology

Biography:

Liu is a Law Review executive with multi-faceted background encompassing international policy research. Developed specialties in editorial planning, global academic marketing strategy, and social science scholarship. Managed multiple projects simultaneously and efficiently by overseeing the daily operations of 17 research programs worldwide. Proven ability to develop strong relationships across cultures and to provide decisive team leadership in a fast-paced environment.

Comments on why I want to be on the RISC-V Board of Directors:

RISC-V and architecture for chip design to realize social justice on a global scale. I would provide my share of efforts in the area of technology policy to build a community that delivers the hardware and standards that create a computational democracy.

Jesús Labarta

Director of the Computer Sciences Department, Barcelona Supercomputing Center (BSC)

Biography:

Jesús Labarta is full professor of Computer Architecture at UPC since 1990 and was Director of CEPBA-European Center of Parallelism at Barcelona from 1996 to 2005. Since its creation in 2005, he has been the Director of the Computer Sciences Research Department within the Barcelona Supercomputing Center (BSC). Prof. Labarta research areas include programming models and performance analysis tools for parallel, multicore and accelerated systems, with special emphasis in helping application programmers to improve their understanding of their applications performance and to improve programming productivity in the transition towards very large-scale systems. Under his supervision, his research team has been developing performance analysis and prediction tools (Paraver and Dimemas) and pioneering research on advanced analytics applied to performance tools. He lead the POP project doing close to 400 deep performance assesments of HPC codes across Europe, helping users optimize them and gaining insight on their characteristics and needs. He has lead the EPI RISC-V stream, with special interest in exploring the potential of RISC-V in the HPC domain. The RISC-V Vector processor and system software developed by a large and distributed european team under his leadership is proving the huge potential of long vectors in HPC but also many other server application domains.

Comments on why I want to be on the RISC-V Board of Directors:

The experience in the previous period has been positive for me, and I think I can provide a vision from a European research organization and from a new domain (HPC).

Ahmed Saeed Sayed

Assistant Professor, Future University in Egypt

Biography:

Ahmed (Senior Member, IEEE) received his PhD in Electrical Engineering, Faculty of Engineering, Ain shams University. He received his BSc (rank 2nd) and MSc in Electronics and Communications Engineering from the Faculty of Engineering, Helwan University, Egypt. He was a visiting researcher, through the Erasmus Mundus award, at the System and Architecture Lab in the Faculty of Engineering, University of Porto, Portugal in 2013/2014. From 2004 to 2010 he was a teaching assistant in the Department of Electrical Engineering. Currently, he is an assistant professor in the Electrical Engineering Department, and the deputy director of the QA center, Future University in Egypt. Ahmed was a postdoc researcher in the center of nanoelectronics and devices, at the American University in Cairo. In June-July 2018, he was visiting staff at the school of Engineering, University of Central Lancashire, United Kingdom. In April 2016, Ahmed was visiting staff at the Faculty of Engineering, University of Porto, Portugal. He is also a Trainer, Editor, and Digital system designer. Ahmed Assisted and supervised a lot of graduation/commercial projects in theq field of Signal Processing, communication systems implementation, and digital system design. He is a member of the organization/steering committee for the scientific meetings and events held in the Faculty of Engineering. His research interests include low-power implementation of IoT processors, signal processing functions, and wired/wireless communication systems on FPGA and ASIC, signal analysis and modeling in high-speed interconnects, Signal Integrity. Ahmed is a senior member of IEEE and the Egyptian Syndicate of Engineers. He is member in the IEEE Standard for Networked Smart Learning Objects for Online Laboratories. He published papers in many areas including solar cells, IoT the efficient implementation of the DSP blocks on an FPGA. Ahmed is the counsellor of the IEEE-FUE student branch. Also, Ahmed is the representative of RISC-V community for FUE.

Comments on why I want to be on the RISC-V Board of Directors:

To help promoting RISC-V in academia and research as well. Also, to strengthen the link between universities and encourage the development of RISC-V-Based boards.

Stefan Wallentowitz

Professor, Munich University of Applied Sciences

Biography:

Stefan is a professor at Munich University of Applied Sciences. He is a long term advocate and active member of the open source silicon community, most prominent in his role as director of the Free and Open Source Silicon Foundation (FOSSi Foundation). He has been active in various RISC-V projects over the last six years. Stefan was involved in the debug task group and has recently become chair of the RISC-V SIG “Academia & Education”.

Comments on why I want to be on the RISC-V Board of Directors:

I was happy to get elected in the last term and over the last term I was able to highlight the role of individual contributors in the process of shaping the RISC-V ecosystem. While the community’s role developed evolutionary, the success of enterprises has changed the way the RISC-V community operates. I am confident that I can help shaping a cooperative framework of community contributors and company contributors, to the overall gain of the RISC-V vision. As a concrete plan I have discussed before about better visibility of gaps in the standardization, development and cooperation procedures, for example in the form of a rather fine grain ticket system, that motivates community members to pick up smaller up to medium tasks in their area of expertise. I would be happy if you elect me into a second term to continue this work, and happy to support anyone you may feel can do a better job and continuing this work.

Robert Kingsly Amalathas

Director & Principal Engineer, Sydaap Technologies LLC

Biography:

Post Graduate in Applied Electronics from Guindy Engineering College, Anna University – India. Over two decades of experience across the length and breadth of the semiconductor industry, having worked with large multinationals and start-up organizations with responsibilities of an Individual contributor and Engineering Management.

Expertise & Skill Sets : ASIC & FPGA Design, Emulation & Validation.
SOC Architectures : Server Processor, Digital TV & Set Top Box, Wireless Application Processor
Ethernet and Storage Chipsets.

Self Owned Digital IP Cores:
http://sydaap.com/products/digital-ip-cores/#Turbo-Decoder-LTE-A
http://sydaap.com/products/digital-ip-cores/#LDPC-Coder-Decoder
http://sydaap.com/products/digital-ip-cores/#FFT-IFFT

Comments on why I want to be on the RISC-V Board of Directors:

Contribute to the revision of RISC-V standards and features and remain synchronized with the industry’s systems and application requirements.
Establish synergy among various partners and stakeholders of the RISC-V forum.

Dhiraj Wohra

Managing Partner

Biography:

20 years in the industry, with involvement in design, products, services, IoT, data sciences & management, manufacturing, and automation. Worked with the best people across Americas, Europe, MEA, and APAC, in various industry sectors, specializing in strategy, scale manufacturing, sales/marketing/GTM and agile projects management plus deployment. Invested interest in startups and technically strong commercial leader with capability to be hands on across highly complex systems, architectures and processes.

Comments on why I want to be on the RISC-V Board of Directors:

My belief that I carry a rounded perspective from technology, commercial to grass-root innovation, can help the RISC-V open source ISA grow and expand more. The industry exposure in last 20 years has been quite enlightening, from manufacturing, financials, healthcare to technology, thus allowing to have meaning conversations with various groups. Further my belief of simplifying complex perspectives helps to disentangle complexities, and a highly involved private/governmental/institutional network may be able to provide a backbone for my engagement with RISC-V. Moreover, I am exploring SoC/FPGA/XPU designing in form a commercial enterprise, thus it may help me expand my network and direction to a full fledged design house in the future.