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RISC-V: An Open Standard Instruction Set Architecture

By Mark Himelstein, CTO of RISC-V International

In this blog post, we’ll explain why RISC-V is an open standard instruction set architecture (ISA). We’ve received some questions about whether RISC-V is open source or an open standard, so this will offer some clarity. 

Anyone can adopt an open standard, although there are mechanisms (Profiles) to ensure interoperability. 

Think of us exactly how you think of Wi-Fi or Bluetooth or TCP/IP. The ISA is the protocol between software and hardware. Like other standards, it is essential that the industry builds on a shared open global standard so that the many stakeholders engaged in the effort can work cohesively across the RISC-V ecosystem.

As we celebrate the 13th anniversary of the founding of RISC-V, it’s incredible to think back about how far we have come. The community has grown from a small group of enthusiasts to 3,570+ members collaborating across 70 countries, and RISC-V members have shipped 10s of billions cores across a wide variety of segments for profit. As we like to say, the open standard RISC-V ISA is everywhere.

RISC-V International produces specifications. We do not provide any implementation of RISC-V in hardware. This is on purpose. We do not want any favoritism among implementations.

RISC-V implementers create their own hardware or simulator software that is compatible with the RISC-V ISA specifications. Those implementations may be open source or commercial.

The RISC-V community is working together to create ISA and non-ISA specifications, implementations of those specs on simulators, and fostering the software ecosystem. This includes both commercial and open-source software, and it also includes how RISC-V system components work (that are not part of the ISA) like IOMMUs or Trusted Execution Environments.

RISC-V encourages individuality, differentiation, and customization, whether it be in how the ISA is implemented or in adding custom instructions to the ISA. Often what starts as a vendor-specific custom set of instructions eventually becomes part of the standard. One recent example is conditional operations.

Collaboration is critical to our shared success. Just as we encourage collaboration within our community, RISC-V works very closely with other nonprofit organizations and open source projects. Examples include OpenHW Group, CHIPS Alliance, and lowRISC. These organizations provide open source implementations of the RISC-V ISA. Examples of projects include GCC, LLVM, Linux, and Khronos, which govern open source products. While RISC-V does not own these products, RISC-V fosters the products driven by these groups (including recruiting resources, sharing roadmaps, etc.), while these groups govern the development and release of RISC-V support in their products.

RISC-V benefits greatly from the rich history of open source. Linux grew thanks to the open source community, and it is impossible to measure the incredible value of it being open and developers feeling that it is their house and belongs to everyone. RISC-V was also developed in the open and RISC-V members can count on RISC-V as their house.

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