Workshop features more than 30 tutorials, presentations, networking receptions and a tour of the Barcelona Supercomputing Center
WHAT: RISC-V Workshop in Barcelona, Spain
WHEN: Monday, May 7 to Wednesday, May 9, 2018
DETAILS: Co-hosted by the Barcelona Supercomputing Center and the Universitat Politècnica de Catalunya (UPC), the RISC-V Workshop in Barcelona gathers the RISC-V ecosystem to share notable RISC-V updates, projects and implementations. Born in academia and research, the RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
Keynote sessions will include Robert Oshana, vice president of software engineering research and development at NXP, Martin Fink, executive vice president and chief technology officer at Western Digital, and Mateo Valero, director at the Barcelona Supercomputing Center. The event schedule is as follows:
- Monday, May 7, 2018: A half-day of tutorials from the working groups of the RISC-V technical committee. The sessions will cover topics such as base ISA ratification, BitManip, compliance, debug, formal spec, memory model, opcode space management, privilege spec, security, software toolchain and vector extensions.
- Tuesday, May 8 and Wednesday, May 9, 2018: Two full days of presentations on RISC-V architecture, commercial and open-source implementations, software and silicon, vectors and security, applications and accelerators, simulation infrastructure and more.
The RISC-V Foundation will also be hosting a networking reception with poster sessions and demonstrations. The reception will feature the latest RISC-V implementations and innovations on the market. In addition, attendees can join one of several tours of the Barcelona Supercomputing Center during the networking reception. The BSC is located in a former chapel and was featured in Dan Brown’s The Da Vinci Code. The full agenda is included here.
To register for the event and learn more about sponsorship opportunities, please visit: https://tmt.knect365.com/risc-v-workshop-barcelona/
For press interested in attending, please email: firstname.lastname@example.org to receive your complimentary pass.
About RISC-V Foundation
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 100 member organizations building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.