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RISC-V SoftCPU Contest

By October 8, 2018October 1st, 2020No Comments

RISC-V SoftCPU Contest: Thank you for your participation

Update: The winners have been announced!


The RISC-V Foundation is proud to announce a RISC-V soft CPU core design contest sponsored by Google, Antmicro, Lattice Semiconductor and Microsemi, a subsidiary of Microchip, Founding Platinum members of the RISC-V Foundation.
The aim of the contest is to further promote the use of the vendor-independent, modular and reusable ISA in FPGA applications, and push the limits of state-of-the-art design by encouraging innovative FPGA soft CPU implementations of the RISC-V ISA.
The contest targets two FPGA platforms from RISC-V Foundation members Microsemi and Lattice Semiconductor. Participants have the option of using the larger 25K LUT Microsemi IGLOO™2 or SmartFusion™2, or the 5K LUT Lattice iCE40 UltraPlus™. The contest challenges contest participants to build either very small or high-performance soft RISC-V implementations, with additional points awarded for novel approaches to the implementation itself.


The entries will be RV32I-compliant soft CPUs. The core can support other standard extensions (e.g. ‘C’ or ‘M’) if the designers decide to do so.
Update: After feedback from the community, we have decided to make implementing the following instructions optional:


We understand that some participants put effort into making these instructions work, so the test suite will still test for compliance with these instructions. However, failure on these tests will not prevent entry. Special consideration will be given to designs which pass all tests (including the optional ones) during the manual judging section.
We apologize for any inconvenience this change might have caused. We appreciate the feedback we have received so far and will incorporate these learnings for any future contests. This process has also highlighted potential improvements that can be done to the current compliance suite. We hope to see this happen in the near future!

Categories & Scoring

There are four categories the entries will compete in:

  • Smallest Microsemi SmartFusion®2 or IGLOO®2 implementation
  • Smallest Lattice iCE40 UltraPlus™ implementation
  • Highest-performance Microsemi SmartFusion®2 or IGLOO®2 implementation
  • Highest-performance Lattice iCE40 UltraPlus™ implementation

For the “smallest implementation” categories, the smallest number of total resources used is better. Total resources shall include Logic Elements, Math Blocks and internal RAM. In case of a draw, the entry with the higher performance is ranked higher.
For the “highest-performance implementation” categories, the performance of the entries will be measured using the Dhrystone benchmark compiled with the -O3 -fno-inline option.
50, 30 and 10 points will be awarded to any entry that ranks 1st, 2nd and 3rd in each category, respectively (so for example, if a given entry is the 2nd smallest on the Microsemi platform, it will be awarded 30 points). An entry targeting both the Microsemi and Lattice platforms can potentially be awarded points in categories for both vendors, if necessary files and instructions to reproduce are provided for both.
An additional pool of 100 points will be distributed between projects by a panel of five judges, selected from the members of the RISC-V Foundation, awarding up to 20 points each based on the creativeness of the entries submitted – participants are encouraged to try out novel approaches to creating their cores.

Minimum Requirements

The resulting design must be in Verilog (the core itself can be written in a framework such as Chisel, SpinalHDL or MiGen which generates Verilog) and be possible to be simulated using Verilator. The design must be a complete FPGA implementation targeting at least one of the two platforms and run the provided Zephyr RTOS application. The Zephyr 1.13 release should be used and can only be modified in a way that does not touch the OS core. Any modifications to the standard RISC-V GCC provided by Zephyr are strictly forbidden.
The CPU must pass the RISC-V RV32I compliance tests.
Also, the CPU must boot the following Zephyr applications:

Entries have to be submitted in the form of repositories on with a clearly stated BSD-style license (the Apache 2.0 license is preferred) including:

  • the Soft CPU’s HDL code
  • constraint and other FPGA-related files necessary to produce a binary bitstream for the respective hardware
  • a README with a complete list instructions and prerequisites, as well as Makefiles or other scripts, needed to produce the bitstream. The README should also include instructions how to simulate the design in Verilator.
  • a binary version of the bitstream which can be fully and identically reproduced using the files and instructions mentioned above
  • any necessary Zephyr 1.13 files in the zephyr/ subdirectory (can be a git submodule)


Image result for microsemi logo
Microsemi IGLOO2 M2GL025/SmartFusion2 M2S025
25K 4-input LUTs
SmartFusion2 boards can be purchased from Future Electronics for $99.95.
Both boards feature the same 25K LUT FPGA fabric. SmartFusion2 is essentially identical to Igloo2 except that it is a SoC FPGA with a built-in Cortex-M3 hard CPU – the soft CPU to be designed should not use the hard CPU subsystems as such but interesting ways to enhance the design using the built-in hard CPU can be implemented.

Lattice iCE40 Ultra Plus – iCE40UP5K
5K 4-input LUTs
There are several boards with this part that can be used for the development:

NEW! There are 30 Lattice iCE40 UltraPlus based Gnarly Grey boards that will be provided with free shipping to the first 30 participants requesting one, starting on Nov. 7. Please email with your full name, mailing address and phone number if you are interested in receiving one.


1st prize: USD $6,000
2nd prize: USD $3,000 + Splash Kit + iCE40 UltraPlus MDP
3rd prize: USD $1,000 + PolarFire Evaluation Kit + iCE40 UltraPlus Breakout Board
NEW! There’s an additional USD $3,000 Creativity prize that will be awarded to the entry judged to be most creative by the judge panel (independent of the points awarded to the entry).


Entries with links to the relevant GitHub repositories will be accepted at by Nov. 26, 2018 at 11:59 p.m. PST.
Results will be announced at the 1st RISC-V Summit taking place in Santa Clara, Calif. from Dec. 3-6. Participants are not required to attend the RISC-V Summit to win. You can check out the agenda for the RISC-V Summit here and register here.

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