WHAT: The RISC-V Foundation will be hosting a series of free “Getting Started with RISC-V” events across North America.
WHERE: The Conference Center at Waltham in Boston, Mass.; Commons Conference Center in Austin, Texas; AV Irvine in Irvine, Calif.; Western Digital in Milpitas, Calif.
WHEN: Monday, April 1 to Thursday, April 4, 2019
DETAILS: The RISC-V Foundation in collaboration with the Linux Foundation is hosting a series of free, half-day “Getting Started with RISC-V” events to showcase innovative RISC-V implementations from members of the RISC-V Foundation. These half-day events will feature RISC-V Foundation members Andes Technology, Antmicro, Dover Microsystems, Hex Five Security, Imperas, Microchip Technology, SiFive and Western Digital.
Getting Started with RISC-V Agenda
- 8:30 a.m. – 9:00 a.m. PT: Welcome and Check in
- 9:00 a.m. – 9:15 a.m. PT: What is RISC-V?, RISC-V Foundation
- 9:15 a.m. – 9:35 a.m. PT: Platform Security–A Detailed Comparison of RISC-V to ARM’s TrustZone, Hex Five Security
- 9:35 a.m. – 9:55 a.m. PT: Bring Real-Time to Linux with RISC-V Based SoC FPGA, Microchip Technology
- 9:55 a.m. – 10:15 a.m. PT: Hardware/Software Co-Design with the Open Source Renode Framework and RISC-V, Antmicro
- 10:15 a.m. – 10:30 a.m. PT: Break
- 10:30 a.m. – 10:50 a.m. PT: Taking RISC-V into High-Performance Sockets with Custom Instructions, Andes Technology
- 10:50 a.m. – 11:10 a.m. PT: Custom Instructions and Architecture Optimization for RISC-V, Imperas
- 11:10 a.m. – 11:30 a.m. PT: Is There a Hole in Your RISC-V Security Stack?, Dover Microsystems
- 11:30 a.m. – 11:45 a.m. PT: Break
- 11:45 a.m. – 12:05 p.m. PT – SweRV Core, Production Grade, Open Source RISC-V Core, Western Digital
- 12:05 p.m. – 12:25 p.m. PT – Innovation Unleashed: Solutions and Silicon Enabling the Intelligent Edge and Linux, SiFive
- 12:25 p.m. – 1:15 p.m. PT – Lunch
Please note that each event is admission free, see below to register.
- Boston: April 1 at the Conference Center at Waltham – please register: here.
- Austin: April 2 at the Commons Conference Center – please register: here.
- Irvine: April 3 at AV Irvine – please register: here.
- San Francisco Bay Area: April 4 at Western Digital in Milpitas– please register: here.
For press interested in attending and scheduling meetings with the RISC-V Foundation and member companies, please email: firstname.lastname@example.org.
To learn more about the RISC-V Foundation, the free and open RISC-V architecture and membership information, please visit: https://riscv.org.
About RISC-V Foundation
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 235 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.
Racepoint Global for RISC-V Foundation
Phone: +1 (415) 694-6700