RISC-V SoftCPU Contest
The RISC-V Foundation is excited to unveil our RISC-V Soft CPU contest sponsored by RISC-V Foundation members Microchip Technology and Thales.
The aim of the contest is to challenge designers to develop a hardware secure RISC-V soft CPU solution that can thwart malicious software security attacks. The contest targets the Creative Development Board using Microchip’s 25K LUT IGLOO™ 2 FPGA available at Future Electronics for $149.95.
The entries should be RV32IMC-compliant soft CPUs and must be publicly released. To ensure compatibility, the design must run the application code on Zephyr and provided on the reference implementation. Developers are permitted to make modifications to the compilers but are encouraged to make as few changes as possible.
This contest is void where prohibited by law. To be eligible to submit an entry you must be over the age of 18 and have reached the age of majority in the jurisdiction in which you reside as of the date of entry. You represent and warrant that you satisfy all eligibility requirements and have participated in the contest in accordance with all applicable laws.
Categories & Scoring
Thales will evaluate the nominations and select the top three winners overall. Judges will review how many of five security attacks are thwarted, in addition to evaluating the total resources used, including logic elements, math blocks and internal RAM, as well as CPU core FMAX dependence on power delivery, expected power consumption and the amount of changes to the compiler.
During the judging process, the criteria will be weighted according to the following percentages:
- How many of the five security attacks are thwarted: 40%
- The total resources used, including logic elements, math blocks and internal RAM: 15%
- The Fmax of the implementation: 15%
- The expected power calculator consumption: 15%
- Amount of changes to the compiler: 15%
Judges encourage participants to make as few modifications as possible to the compiler for a higher overall score.
For more details about the five security attacks, Zephyr RTOS and the application code, please visit GitHub.
The resulting design must be in Verilog (the core itself can be written in a framework such as Chisel, SpinalHDL or Migen which generates Verilog) and be possible to be simulated using Verilator. The design must be a complete FPGA implementation targeting Zephyr RTOS application. The Zephyr 1.14 release should be used and can only be modified in a way that does not touch the OS infrastructure. Modifications to a compiler are allowed but not required.
The deadline for entries is Sept. 15, 2019 at Midnight CET. To submit, contest participants must email firstname.lastname@example.org with links to their relevant GitHub repositories, including the zipped FPGA files and compiler.
The contest results will be announced at the Getting Started with RISC-V event in Paris on Sept. 24, 2019. Contest participants do not have to be in attendance to be eligible to win. To learn more about the Getting Started with RISC-V European roadshow and register, please visit: https://events.linuxfoundation.org/events/risc-v-europe-roadshow-2019/.