ZURICH – Dec. 7, 2021 – RISC-V International, a global open hardware standards organization, today announced that Syntacore, a semiconductor IP company specializing in customizable microprocessor cores and tools based on the RISC-V instruction set, has upgraded to the Premier membership level. At this Premier level, Alexander Redkin, CEO and co-founder at Syntacore, will join the RISC-V Board of Directors.
A founding member of RISC-V International, Syntacore focuses solely on the RISC-V ISA and was one of the first companies to sample commercial RISC-V SCR3-based system-on-chips (SoCs) in early 2016. Syntacore’s upgrade to the Premier membership level demonstrates the company’s commitment to RISC-V, and the expansive ecosystem of current and prospective customers it serves.
“As a founding RISC-V member, we’ve evolved and matured alongside the RISC-V ISA as a company. Today’s announcement further strengthens our leadership position in the RISC-V IP market with continued momentum across many global markets into the new year and beyond,” said Alexander Redkin, Director at Syntacore. “All of our IP is fully compatible with the latest versions of the RISC-V specifications and with our turnkey customization services, our customers are able to witness the power and flexibility of the RISC-V architecture across many of today’s most compute-intensive applications.”
Syntacore is a RISC-V processor IP specialist creating flexible, highly-efficient microprocessor cores that help customers to design unique solutions for a wide range of vertical markets – from the IoT and data storage and processing to embedded systems and cognitive, machine learning, and artificial intelligence applications.
“The work Syntacore has done over the years to accelerate and improve its processors, alongside the RISC-V spec, has enabled our ecosystem to expand globally,” said Calista Redmond, CEO of RISC-V International. “The company’s upgrade to Premier membership further champions Syntacore in the RISC-V world and I’m excited to see new developments and projects hitting the market soon from this team.”
Syntacore is speaking and exhibiting at the RISC-V Summit, which is taking place from Dec. 6 – 8, 2021 in San Francisco and virtually. Syntacore’s John Hartley will be presenting the session “RISC-V Compatible Processor IP by Syntacore: Compact Open-source MCU to Multicore Linux” on Tuesday, Dec. 7 at 10:30 a.m. PT, and Sergey Yakushkin will be giving the demo “Debian Linux at Octacore SCR7-based SDK” on Wednesday, Dec. 8 at 3:20 p.m. PT. Attendees are also welcome to stop by Syntacore’s booth #B9 in the Expo Hall.
To learn more about Syntacore, please visit: https://syntacore.com/.
About RISC-V International
RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration. RISC-V International comprises more than 2,400 members building the first open, collaborative community of software and hardware innovators powering an open era of processor innovation. The RISC-V ISA delivers a new level of free, extensible software and modular hardware, paving the way for the next 50 years of open computing design freedom and innovation.