A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores

In this Synopsys webinar, presenters from SiFive will share the advantages of Synopsys Formality ECO on their overall ECO cycle which has enhanced patching capabilities and resulted in faster verification runtime leading to improved TAT. With the retimed and flattened design, it is difficult to generate the sizable patch for fast CPUs designs targeted by SiFive. SiFive designs have strict requirements on the patch size, patch affecting hierarchies, changes applicable to RTL and ease of implementation at route_opt stage. By using Synopsys Formality ECO suite, SiFive has been able to generate a hassle-free patch and verify it 3-5x faster than traditional formal verification ensuring performance of the CPU.