Design and Management Strategies for Hardware Accelerators

As Dennard scaling ends, the pursuit of specialized hardware has become prevalent. Architects have embraced various technologies, such as high-level synthesis and reconfigurable fabrics (e.g., FPGAs), to reduce accelerators’ costs. Efficient hardware acceleration, however, remains challenging due to the effort required to understand and optimize the design and limited system support for efficient run-time management. This talk focuses on reducing costs and complexities of developing and using reconfigurable hardware accelerators by introducing intelligent design mechanisms and efficient run-time management policies. In this talk, I will describe our automated framework, called Prospector, that uses statistical learning to further reduce design costs via high-level synthesis. Prospector uses Bayesian techniques to optimize synthesis directives and discover Pareto-efficient designs in complex multi-objective design spaces more quickly. Furthermore, I will present our Spatiotemporal FPGA Scheduling, that re-thinks traditional scheduling policies to account for unique characteristics of modern FPGAs to achieve long-term target allocations while improving resource utilization for collocated reconfigurable accelerators.

Registration required.