Skip to main content
Loading Events

« All Events

  • This event has passed.

How to Exhaustively Verify that Your Custom Instructions Aren’t Secretly Breaking Your RISC-V Design

October 24, 2023 @ 8:00 am - 9:00 am PDT


The last thing you want to do when adding custom instructions to your RISC-V design is to unintentionally insert some deep corner case bug – the kind of bug that’s discovered by your customers a month after the end-product has shipped.

Simulation-based verification approaches find many common errors; but to be really sure that there are no hidden side-effects or “specification bugs”, an exhaustive, formal-based verification flow is also needed.

In this presentation we will guide you through the simple design and verification steps you can take to combine simulation and formal approaches; with a particular emphasis on leveraging automated, formal-based sequential equivalence checking (SLEC). These methodologies will be illustrated with real-world case studies.

This is a joint webinar with Codasip – a Custom Compute and
RISC-V leader.


What You Will Learn:

  • RISC-V customization principles
  • An efficient design automation and customization flow for RISC-V processors
    • Processor design in a high-level description language
    • Going from high-level description language to RTL generation
  • A light-weight formal verification flow targeted towards customization

Who Should Attend:

  • Design engineers
  • Design verification engineers
  • Formal verification engineers
  • Verification managers
  • RISC-V enthusiasts

What/Which Products are Covered: 

  • Codasip Studio design automation toolset
  • Codasip CodAL processor description language
  • Codasip L31 RISC-V embedded processor
  • Siemens Questa OneSpin Processor Verification App


October 24, 2023
8:00 am - 9:00 am PDT
Event Category:
Event Tags:


View Organizer Website


Name of Event Contact for Questions
Tora Fridholm
Email of Contact for Questions
Member Organization Hosting Event

Stay Connected With RISC-V

We send occasional news about RISC-V technical progress, news, and events.