The Symposium will feature selected presentations and panel sessions as well as advanced VLSI technology developments, innovative circuit designs, and the applications they enable, such as artificial intelligence, machine learning,...
Abstract: VerifAI Inc. has pioneered the world's first 'AI Test Engineer' called TestGuru which leverages Multiple Large Language Models (LLMs), Reinforcement Learning (RL), and Formal Methods to find and fix...
Learn More and RSVP Abstract: VerifAI Inc. has pioneered the world's first 'AI Test Engineer' called TestGuru which leverages Multiple Large Language Models (LLMs), Reinforcement Learning (RL), and Formal Methods to find and fix...
Virtual Event - This talk covers issues, strategies, and experiences with RISC-V SoCs, highlighting challenges and solutions. Learn More
Learn More & RSVP Join us for a 30 min interactive discussion where you will hear from industry leaders and your peers about: The RISC-V standard, and why you should...
The Design Automation Conference (DAC) is recognized as the premier event for the design and design automation of electronic chips to systems. DAC offers outstanding training, education, exhibits and superb...
The RISC-V Summit Europe is the premier event that connects the European movers and shakers - from industry, government, research, academia and ecosystem support - that are building the future of innovation...
The kind folks at Diogenes Makerspace are allowing us to host a monthly Hackathon on the 4th Tuesday of the month at 7pm. Come on by to meet with other...
The openSUSE Conference is an annual gathering of openSUSE Project and Open Source Communities. Known as oSC, it features a blend of virtual and in-person presentations as well as workshops...
The expected purpose of establishing a biweekly synchronization mechanism: Help partners in East Asia and Australia time zones communicate with each other about progress and needs. Communicate in Chinese video...
RISC-V Open Hours provides the opportunity for the community to interact outside of the bounds of mailing lists, with a particular focus on RISC-V support in open source software projects...
The expected purpose of establishing a biweekly synchronization mechanism: Help partners in East Asia and Australia time zones communicate with each other about progress and needs. Communicate in Chinese video...
We send occasional news about RISC-V technical progress, news, and events.
