RISC-V Ecosystem News

SiFive Builds Hardware Crypto and Security for RISC V SoCs | Sebastian Grüner, Golem

Sifive’s RISC V specialists are committed to providing crypto engines, key management, storage isolation and many more security features in their SoC designs. The Sifive Shield initiative is ambitious and offers competition to modern ARM and x86 chips.article (in German): https://www.golem.de/news/shield-sifive-baut-hardware-crypto-und-security-fuer-risc-v-socs-1910-144604.html

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OneSpin Shows How to Achieve IC Integrity at DVCon Europe | OneSpin

OneSpin’s verification experts present RISC-V integrity tutorial and functional safety sessionMUNICH, GERMANY –– October 24, 2019 –– OneSpin® Solutions, provider of certified IC integrity verification solutions for building functionally correct, safe, secure and trusted integrated circuits, will present its verification expertise through a tutorial, technical session and an exhibit at DVCon Europe, being held October 29 – 30, 2019 at the Holiday Inn Munich City Centre, Munich, Germany.article: https://www.onespin.com/press-events/press-releases/details/news/detail/News/onespin-shows-how-to-achieve-ic-integrity-at-dvcon-europe/

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RISC-V Challenges and Opportunities | Ed Sperling, Semiconductor Engineering

Semiconductor Engineering sat down to discuss open instruction set hardware and the future of RISC-V with Ben Levine, senior director of product management in Rambus’ Security Division; Jerry Ardizzone, vice president of worldwide sales at Codasip; Megan Wachs, vice president of engineering at SiFive; and Rishiyur Nikhil, CTO of Bluespec. What follows are excerpts of that conversation.article: https://semiengineering.com/risc-v-challenges-and-opportunities/

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SiFive Shield: An Open, Scalable Platform Architecture for Security | James Prior, SiFive

SiFive Shield is an open, scalable platform architecture designed to enable whole SoC security for RISC-V designs. The needs of modern SoC design dictate the need for a scalable solution for security, offering a low trusted computing base with clear root-of-trust and crucially, is auditable. Customization is also key, as a single offering fits all approach does not align to the needs of the next generation of domain specific processors…

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GCC Support for the Draft Bit Manipulation Extension for RISC-V | Maxim Blinov, Embescom

One of the currently proposed draft ISA extensions for RISC-V is the Bit Manipulation Instructions extension (from henceonwards referred to as the “Bitmanip” or “BMI” extension.) It proposes to provide fast and direct instructions for commonly-used bitwise operations, often found in cryptographic, logarithmic, bit-counting, and logical operations. The GCC toolchain work has been developed by the community with contributions from SiFive and myself at Embecosm, providing bug fixes, regression tests,…

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LLVM Support for the Draft Bit Manipulation Extension for RISC-V | Paolo Savini, Embecosm

The RISC-V Instruction Set Manual describes the current status of the RISC-V ISA and its extensions. Among these there’s a mention of the ‘B’ extension that is meant to host specific instructions for bit manipulation operations.A well known proposal for such extension comes from Clifford Wolf and can be found here.We implemented an extension of the RISC-V back end of LLVM based on such proposal that is now available on the Embecosm GitHub…

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Real-Time Visualization Of RISC-V Systems | Joachim Kroll, Elektronik

Segger’s debugging tool SystemView now enables real-time visualization of RISC-V processors.By using its real-time recording and visualization capabilities, SystemView is able to represent the actual runtime behavior of an application. For continuous real-time recording and live analysis, the program uses the debug adapter J-Link and Segger’s Real-Time Transfer (RTT) technology.article (in German/auf Deutsch): https://www.elektroniknet.de/design-elektronik/embedded/echtzeit-visualisierung-von-risc-v-systemen-170219.html

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Why RISC-V Will Prevail | Marc Sauter, Golem

At lunch at the RISC-V workshop in Zurich, Krste Asanovic succinctly answers the initial question: “RISC-V is called that because it is our fifth major RISC architecture.” Asanovic must know, because the Berkeley University professor is co-inventor of the Open CPU (Open Hardware ISA) architecture. It was designed in 2010 together with RISC veteran David Petterson and made available in 2014.article (in German / auf Deutsch): https://www.golem.de/news/offene-prozessor-isa-wieso-risc-v-sich-durchsetzen-wird-1910-141978.html

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LLVM Clang RISC-V Now Supports LTO | Michael Larabel, Phoronix

With the recent release of LLVM 9.0 the RISC-V back-end was promoted from an experimental CPU back-end to being made “official” for this royalty-free CPU ISA. Work though isn’t over on the LLVM RISC-V support with new features continuing to land, like link-time optimizations (LTO) most recently being enabled within the Clang 10 code.article: https://www.phoronix.com/scan.php?page=news_item&px=RISC-V-LLVM-Clang-LTO

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