RISC-V News

RISC-V Enters Mainstream at Embedded World 2017

Berkeley, California – Over the last year the RISC-V architecture has evolved from an academic research interest to a mainstream embedded processor technology with a rich ecosystem and a fast-growing number of real-world implementations. As a sign of this progress, a number of companies will be demonstrating commercial implementations of RISC-V products next week at Embedded World 2017, the leading international trade fair for embedded systems (March 14-16, Nuremberg, Germany) https://www.embedded-world.de/enRISC-V…

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RISC-V chosen as Best Technology of 2016

The Linley Group Announces Winners of Annual Analysts’ Choice Awards   In a news release issued today, January 12th, 2017, The Linley Group today announced the winners of its annual Analysts’ Choice Awards which recognize the top semiconductor products of 2016 in seven categories: embedded processors, mobile processors, server processors, processor-IP cores, mobile chip, networking chip, and best technology.  The RISC-V Instruction Set Architecture was selected as the Best Technology of 2016.In…

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RISC-V Foundation Appoints Board of Directors

RISC-V Foundation appoints inaugural Board of Directors Seven Directors Appointed to the BoardBerkeley, CA, June 9, 2016 – Today, the RISC-V Foundation is pleased to announce the Foundation’s inaugural Board of Directors.  Seven industry veterans with varied career experience within large multinational companies, smaller startup companies, non-profit organizations and academia have been appointed to serve on the RISC-V Foundation Board of Directors.The inaugural set of Directors include: Krste Asanović as…

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RISC-V Offers Simple, Modular ISA

  The RISC-V ISA has been featured in the latest edition of the Microprocessor Report written by David Kanter of The Linley Group.The RISC-V Foundation has retained distribution rights for this report.  The full report is shown below and it can be downloaded and freely distributed.  

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Charting a New Course for Semiconductors

The Global Semiconductor Alliance has released a new report “Charting a New Course for Semiconductors” which explores the future of the semiconductor industry and asks “Is RISC-V the new Linux?”.                               Global Semiconductor Alliance Releases New ReportThe report includes 4 Chapters covering key areas including: Chapter 1 – An Industry in Transition – Rising development costs, decreasing margins and…

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RISC-V Draft Compressed ISA version 1.9 released

The RISC-V Compressed Instruction Set Manual Version 1.9 Draft proposal has been released and is available at this link.  You can also download a PDF version at this link.We welcome community feedback and comments on this draft. We believe this draft represents the close to final design for RV32C and RV64C (it seems premature to freeze R128C), though we are requesting one more round of comments, hence the 1.9 revision…

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RISC-V in Verilog

V-scale, an implementation of an RV32IM core in Verilog has been released and is available at: https://github.com/ucb-bar/vscale.This core implements a simple, Z-scale-class pipeline, and is designed for integration with either existing microcontroller-class bus interconnects or the Rocket chip generator. The build infrastructure for both flows will be publicly released with an upcoming update to the platform of small RISC-V systems compatible with Z-scale.

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RISC-V Foundation Incorporated!

The RISC-V Foundation has been officially incorporated! For more information about joining the RISC-V Foundation, please contact Rick O’Connor, Executive Director via email at rickoco@riscv.org.

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RISC-V Draft Compressed ISA Version 1.7 Released

The RISC-V Compressed Instruction Set Manual Version 1.7 Draft proposal has been released and is available at this link. You can also download a PDF version at this link.We welcome community feedback and comments on this draft. In particular, we offer two options of what RVC should be. Thus, we need your feedback in order to decide which path to take. (The report lists the pros and cons of each…

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