RISC-V Ecosystem News

Bluespec To Co-Host SiFive Technical Symposium

Bluespec is pleased to announce it will be co-hosting the Boston RISC-V Technical Symposium, an opportunity to engage with the RISC-V community that is revolutionizing processor innovation through open source collaboration. The event, occurring February 28 in Boston, is a great opportunity for attendees to explore the global phenomenon of RISC-V and the countless creative solutions it is spurring. It is one of the 50+ trailblazing RISC-V symposiums being held…

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OneSpin Launches First Formal RISC-V Integrity Verification Solution

OneSpin Solutions, provider of innovative verification solutions for highly reliable, digital integrated circuits (ICs), today unleashed its RISC-V Integrity Verification Solution for development and assessment of RISC-V cores, leveraging its advanced formal verification expertise for automotive and other high-integrity processor applications.The RISC-V Integrity Verification Solution, based on the RISC-V instruction set architecture (ISA) formalized in a set of SystemVerilog Assertions (SVA), is delivered as a series of formal applications (Apps)…

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EE Times Article: UltraSoC Extends Monitoring To ‘See’ Into Complex ML, AI Chips

UltraSoC has extended its on-chip analytics architecture to provide monitoring and analytics of complex machine learning (ML), artificial intelligence (AI), and parallel computing chips comprising up to 65,536 elements. The new architecture, to be introduced in the company’s UltraDevelop 2 integrated development environment (IDE), allows system-on-chip (SoC) designers to build on-chip monitoring and analytics systems with up to 65,536 elements, allowing seamless support for systems with many thousands of processors. This…

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Monoist Article: New Open Source Innovation To Promote RISC-V Development

Western Digital announced three open source innovations including “RISC-V SweRV Core” on Dec. 4, 2018 to promote the development of the ecosystem using RISC-V. They promote the development of specialized computer architecture, such as real time processing and reasoning of big data and fast data.RISC-V SweRV Core is a bidirectional superscalar processor. Multiple instructions can be executed at the same time, with 32 bit, 9 stage pipeline configuration. The expected performance is…

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Root.cz Article: Western Digital Has Released Its RISC-V SweRV Processor As Open Source

Western Digital has released its SweRV processor design using the RISC-V architecture under open-source licensing. You can find the RTL model on GitHub under the Apache 2.0 license, so other manufacturers can benefit from a ready-made design. The license is very loose, in fact only forcing the link to the original creator and prohibiting the use of the Western Digital brand in the title of the derivative work.SweRV is a 32-bit in-order superscalar processor with a nine-stage pipeline…

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AB Open Article: WCH Adds Upcoming RISC-V Bluetooth LE Microcontroller To CH57x Family

Embedded news site CNXSoft has highlighted an upcoming part from Jiangsu Qinheng Co., Ltd, also known as WinChipHead (WCH), which combines a RISC-V core running at 60MHz with Bluetooth Low Energy (BLE) connectivity.Recently added to WCH’s parts list, the 32-bit microcontroller has been dubbed the CH572 – putting it into the same CH57x family as the company’s Arm Cortex-M0 microcontroller offerings – and is claimed to run at 60MHz. Full…

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AB Open Article: RISC-V Workshop Zurich Call For Speakers Now Open

The RISC-V Foundation has issued a call for speakers ahead of the RISC-V Workshop Zurich, scheduled for mid-June 2019, with a submission deadline of the 28th of February.Hosted by the non-profit RISC-V Foundation in partnership with Informa’s Knowledge & Networking Division, KNect365, the RISC-V Workshop Zurich is to be held at ETH Zürich on the 11th to 13th of June 2019 as one of several events around the globe dedicated…

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EE Times Article: RISC-V Eases Innovation In Military/Aerospace Designs

The RISC-V Instruction Set Architecture (ISA), and open hardware standards in general, have the potential to be a real boon the military and aerospace designers.  “RISC-V is being received with open arms by the military and aerospace sectors,” said Tim Morin, director of strategic marketing in Microchip Technology’s FPGA business unit. “They are very excited about it.”From a design perspective, the ISA addresses the need to minimize power consumption, streamline…

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Elektronik Article: Ultra Low Power Processor With RISC-V IoT Processor For AI Applications

RISC-V allows users to extend the instruction set with special instructions for vector processing. For example, to achieve high computing performance, as required for neural networks. Combined with dynamic energy management, this creates a KI-IoT processor for battery operation. What would happen if IoT sensors and devices began to process information-rich signals such as sounds, vibrations and images – that’s what we started getting interested in in 2016. Back then, IoT sensors…

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Elektronik Article: Open Source Hardware RISC-V The Way To Industrial Application

The RISC-V instruction set architecture must be carried out of the academic circle of colleges into the industry in applications to be successful. Prof. Robert Oshana from NXP Semiconductors knows how practical entry can be made for companies. The move from research to industrial application can be an obstacle that should not be underestimated. In particular, industrial companies face the challenge of adapting to existing, established processes and quality standards.A practical approach…

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