What’s New

See Western Digital’s SweRV Core family at the 2021 RISC-V Summit

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RISC-V has been a very popular choice for embedded processor designs. Western Digital’s existing SweRV Core family is among the highest performance, area optimized embedded RISC-V Cores available today. The…

RISC-V Blog

See Western Digital’s SweRV Core family at the 2021 RISC-V Summit

| Blog, What's New | No Comments
RISC-V has been a very popular choice for embedded processor designs. Western Digital’s existing SweRV Core family is among the highest performance, area optimized embedded RISC-V Cores available today. The…

How the Imagination RVfpga: Understanding Computer Architecture course is giving engineering under-grads real-world skills | Robert Owen, Imagination Technologies

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If you were to take a look through the academic materials now available about RISC-V you will find a wealth of information around SoC creation, including inventing special instructions and…

Improving the OpenLane ASIC build flow with open source SystemVerilog support | Antmicro

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Open source toolchains are key to building collaborative ecosystems, welcoming to new approaches, opportunistic/focused innovations and niche use cases. The ASIC design domain, especially in the view of the rising…
Alibaba Cloud

How Alibaba is Porting RISC-V to the Android OS | Guoyin Chen, Alibaba

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With the high performance Alibaba T-Head XuanTie processor coming to market, we believe it will benefit the RISC-V industry to port RISCV to the Android OS. Over the past year,…

In the News

November 24, 2021 in In the News

Samsung-Esperanto Concept AI-SSD Prototype | David Schor, WikiChip Fuse

Earlier this year we’ve detailed Esperanto’s first neural processor, the ET-SoC-1. The company’s approach for accelerating AI workloads involved integrating a large number of tiny RISC-V cores capable of performing…
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November 24, 2021 in In the News

Canonical at RISC-V Summit 2021 | Canonical

RISC-V Summit is an annual conference that showcases the power that open collaboration can have on the processor industry. This year, the event is taking place in San Francisco and…
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November 24, 2021 in In the News

Embedded edge vision development kit for RISC-V FPGA | Nick Flaherty, EE News Europe

The Smart Embedded Vision tool for Microchip’s PolarFire RISC-V FPGA supports vision applications from neural network inferencing to Industrial Internet of Things (IIoT) and factory automation Microchip Technology has launched…
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November 15, 2021 in In the News

Open Hardware: Skyrocketing Momentum & Global Adoption from Embedded to Enterprise | Calista Redmond, RISC-V International

See RISC-V International CEO Calista Redmond's keynote at Open Source Summit 2021 on Open Hardware: Skyrocketing Momentum and Global Adoption from Embedded to Enterprise. Watch the full video. 
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Announcements

September 16, 2021 in Announcements

RISC-V Launches the Open Hardware Diversity Alliance

Founded in Collaboration with the CHIPS Alliance, OpenPOWER Foundation, and Western Digital, the Alliance is Focused on Providing Support Programs, Learning Opportunities, and Mentoring for Women and Underrepresented Individuals in…
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July 28, 2021 in Announcements, What's New

The 2021 RISC-V Summit Will Demonstrate Adoptions and Technical Advances This December in San Francisco

ZURICH and SAN FRANCISCO – July 28, 2021 – RISC-V International announced the 2021 RISC-V Summit that will bring together the open hardware community for three days of deep technical…
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May 5, 2021 in Announcements, What's New

RISC-V International and seL4 Foundation Announce New Security Milestone

SAN FRANCISCO, May 5, 2021 – Today, the seL4 Foundation and RISC-V International announced that the verified seL4 microkernel on the RV64 architecture has been proved down to the executable…
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April 29, 2021 in Announcements

RISC-V International Welcomes Chengwei Capital as a Premier Member

Investment firm Chengwei Capital to join the RISC-V Board of Directors and Technical Steering Committee Zurich – April 29, 2021 – RISC-V International, a non-profit corporation controlled by its members…
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