What’s New

March 5, 2021 in Blog, What's New

RISC-V Execution Stages | Maven Silicon

This video explains the execution stages of a RISC-V processor and how it executes all the instructions. Follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction…
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RISC-V Blog

RISC-V Execution Stages | Maven Silicon

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This video explains the execution stages of a RISC-V processor and how it executes all the instructions. Follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction…

RISC-V Star Rising from the East – Introducing StarFive

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With the recent announcement of BeagleVTM, reported by premium technology media Ars Technica, Tom’s Hardware, CNX Software, as well as many others, a new name has emerged in front of…

RISC-V growth and successes in technology and industry : embedded world 2021

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 RISC-V International has more than 1,000 members across over 50 countries who are working in hardware, software, services, and various industries for a strong and healthy RISC-V ecosystem. It is…

OpenHW Group highlights how verification is a key aspect of the open-source CORE-V processor IP

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The RISC-V ISA (Instruction Set Architecture) permits a range of possibilities for processor implementation with a modular approach for standard and custom extensions. In addition, implementations may be shared commercially…

In the News

March 2, 2021 in In the News

RISC-V Fast Tracks Simpler Extensions | eeJournal, Jim Turley

One of the charming aspects of RISC-V is that it’s so… flexible. As an open-source processor specification, absolutely anyone can use it, modify it, and commercialize it. There are no…
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March 1, 2021 in In the News

Lattice Expands mVision Solutions Stack Capabilities | businesswire

HILLSBORO, Ore.--(BUSINESS WIRE)--Lattice Semiconductor Corporation (NASDAQ: LSCC), the low power programmable leader, launched the latest version of its award-winning solutions stack for low power embedded vision systems, Lattice mVision™ 2.0. The…
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March 1, 2021 in In the News

Imperas Donates Latest RV32/64K Crypto (scalar) Architectural Validation Test Suites to the RISC-V Verification Ecosystem | imperas

Oxford, UK – March 1st, 2021 – Imperas Software Ltd., the leader in RISC-V processor verification technology, today announced the release of the latest update to the RISC-V architectural validation test suites…
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March 1, 2021 in In the News

RISC-V Is On a Roll. Is It Ready to Take a Seat Alongside Intel, AMD, and Arm? | Data Center Knowledge, Christine Hall

RISC-V, the emerging open source instruction set architecture for processors that have so far been used mostly as accelerators, is suddenly on a roll and appears about ready to become competitive in the…
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Announcements

March 2, 2021 in Announcements

Learn About the RISC-V ISA with Two Free Training Courses from The Linux Foundation and RISC-V International

The online courses are offered on edX.org and will make RISC-V training more accessible SAN FRANCISCO - EMBEDDED WORLD - March 2, 2021 – The Linux Foundation, the non-profit organization…
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February 23, 2021 in Announcements

RISC-V International Unveils Fast Track Architecture Extension Process and Ratifies ZiHintPause Extension

RISC-V International Unveils Fast Track Architecture Extension Process and Ratifies ZiHintPause Extension Fast Track significantly accelerates the ratification of small architecture extensions Zurich – Feb. 23, 2021 – RISC-V International,…
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December 14, 2020 in Announcements

RISC-V International Annual Awards

Each year, RISC-V International recognizes certain members of the community who have gone above and beyond in their dedication and effort with RISC-V. These are the awards for 2020. RISC-V…
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December 8, 2020 in Announcements

Stream Computing Joins RISC-V International as a Premium Member

Silicon startup Stream Computing to join the RISC-V Board of Directors and Technical Steering Committee to advance open source AI innovation Zurich – Dec. 8, 2020 – RISC-V International, a…
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