RISC-V Ecosystem News

In the chip field, RISC-V is an absolutely unique keyword.Unlike its competitors, the instruction set architecture RISC-V is an open, advanced, modular and extensible, especially its own open source properties, so that it will not be subject to the ups and downs of any single company. Driven by these various factors, this instruction set has been popular since 2011, and the past two years have attracted the enthusiastic support for…

The current leading three companies in SoC provide internal analysis and detection technology include: UltraSoC, for its system-on-chip design process; Moortec, for its in-chip monitoring subsystem IP solutions; Arteris for its Ncore cache cohert interconnect IP. These security IP experts who work silently at the bottom of the system network and smart devices are the “ invisible champions ” in the field of SoC chip design .In the recently held RISC-V China tour Shenzhen seminar, UltraSoC company CEO Rupert Baines shared its technical solutions for safety and performance testing of semiconductors, and released specifications…

At present, there are about 300 companies in China that are concerned about or developing with the RISC-V instruction set. In 2018, they have also established the “China RISC-V Industry Alliance” and the “China Open Command Ecosystem (RISC-V) Alliance.” Therefore, many people will naturally think that the driving force of RISC-V architecture and products is more likely to come from China. At the same time, however, some critics believe that…

lowRISC is a not-for-profit, community-driven organisation working to provide a high quality, security-enabling, open SoC base for derivative designs. The organisation is lowering the barrier to producing custom silicon, enabling research and FPGA experimentation, and establishing a vibrant ecosystem around open silicon designs. lowRISC supports a core engineering team who collaborate with industry partners, academic groups, and the wider community to drive the open source silicon ecosystem.“We are very pleased…

A novel RISC-V-based processor architecture is designed to proactively protect against any threats. At 20 Hz, it randomly changes its own code and processed data. Previous update strategies with pushed patches would be superfluous.Morpheus will smash the matrix of hackers! The eponymous processor blocks potential attacks by encrypting and randomly reordering critical bits of its own microcode and data 20 times per second. Even the fastest automated electronic hacking techniques should be overtaxed, not…

Open source silicon promises new challenges and opportunities for both industry and the open source community. To take full advantage of open silicon we will need new design methodologies, new governance models, and increased collaborations between industry, academia, and not for profits. A vibrant free and open source software community has been vital to both Google and our customer’s success. We look forward to supporting the new domain of open…

Google has announced it is increasing its presence in the world of free and open source silicon (FOSSi), extending its partnership with the lowRISC project.Unlike proprietary processors, the design and instruction set architecture (ISA) for which are kept behind a typically expensive licence wall, free and open source silicon (FOSSi) does what it says on the tin: Projects like RISC-V provide both the ISA and key implementations under permissive licences,…

The Parallel Ultra-Low Power (PULP) Platform has announced a partnership between ETH Zurich, Greenwaves Technologies, and Bitcraze to develop a PULP-powered and wireless artificial intelligence module for drone use: the AI Deck.Based on the earlier PULP-Shield, built as part of the PULP-DroNet project, the AI Shield is designed to control a Crazyflie 2.0 micro-drone. The original design partnered GreenWaves’ GAP8 RISC-V system-on-chip with two off-chip memories, a QVGA ultra-low-power camera,…

The construction of electronic components has changed considerably in the last 20 years. Therefore, innovations in processor architectures are expected to lead to changes in the next generation of architectures and to be brought about by RISC-V (Reduced Instruction Set Computing – 5th iteration). There are already a large number of technology companies, semiconductor manufacturers, universities and state organizations that implement and evaluate RISC-V based technology.RISC-V is an open source…

This article by Zvonimir Bandić of Western Digital, introduces the RISC-V-based SweRV core, which builds on the classic five-stage RISC-V pipeline and allows up to two instructions per clock cycle.Since the RISC-V instruction set architecture was unveiled (2015) and RISC-V foundation established (2016), we have seen a flurry of activity: many open source hardware projects, many corporate adoptions of the architecture, fast-growing membership of the foundation, and fast-growing open-source RISC-V…