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RISC-V Sees Significant Growth and Technical Progress in 2022 with Billions of RISC-V Cores in Market

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RISC-V Summit brings together the global RISC-V community after a banner year San Jose, Calif. – Dec. 13, 2022 – RISC-V International, the global open standards organization, highlighted the community’s…

RISC-V Blog

CPU RTL co-simulation in Renode

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Support for co-simulating HDL models in Renode with Verilator has been an integral part of the framework since the 1.7.1 release, introducing a new dimension of flexibility and allowing Renode to…

Xuantie RISC-V TEE solution for MCU

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Author: Lijie Mao 1. Overview TEE (Trusted Execution Enviroment) has been the most widely used method for device security protection. In this article, we will describe a TEE solution based…

RISC-V RV32I RTL Verification using UVM | Maven Silicon Blog

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By: Putta Satish, Principal Engineer, Maven Silicon In this demo video, Putta Satish explains the complete RISC-V DV flow: RISC-V RTL pipeline architecture overview, RISC-V processor verification plan, UVM TB…

The First DSA Agile Development on Open Xuantie RISC-V processor

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Author: Prof. Jun Han, Fudan University T-Head made the Xuantie RISC-V series processors open-source and made a series of tools and system software available at the 2021 Apsara Conference. This…

In the News

February 3, 2023 in In the News

GreenWaves Technologies announces a €20M financing

GreenWaves, the French pioneer in RISC-V application processors for battery powered devices and a performance leader in AI and DSP, announces a 20 million euros financing led by Innovacom together…
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January 30, 2023 in In the News

FOSDEM 2023 schedule – Open-source Embedded, Mobile, IoT, Arm, RISC-V, etc… projects

After two years of taking place exclusively online, FOSDEM 2023 is back in Brussels, Belgium with thousands expected to attend the 2023 version of the “Free and Open Source Developers’ European Meeting”…
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January 30, 2023 in In the News

NASA Recruits Microchip, SiFive, and RISC-V to Develop 12-Core Processor SoC for Autonomous Space Missions

NASA’s JPL (Jet Propulsion Lab) has selected Microchip to design and manufacture the multi-core High Performance Spaceflight Computer (HPSC) microprocessor SoC based on eight RISC-V X280 cores from SiFive with…
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January 30, 2023 in In the News

Espressif adopts RISC-V for next gen EPS32s, adds Wi-Fi 6 and BT 5

Espressif has used RISC-V cores in its latest ESP32 wireless microcontrollers: ESP32-C6 – ICs, modules and SDK imminent Dual RISC-V cores (160MHz + 20MHz), Wi-Fi 6 (2.4GHz), Bluetooth 5 (LE),…
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Announcements

December 23, 2022 in Announcements

RISC-V Honors Outstanding Technical and Community Contributions for 2022

Recipients Selected from Tens of Thousands of Engineers Working on RISC-V Initiatives Globally San Jose, Calif. – Dec. 21, 2022 – RISC-V International, the global open standards organization, announced the…
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December 13, 2022 in Announcements, What's New

RISC-V Sees Significant Growth and Technical Progress in 2022 with Billions of RISC-V Cores in Market

RISC-V Summit brings together the global RISC-V community after a banner year San Jose, Calif. – Dec. 13, 2022 – RISC-V International, the global open standards organization, highlighted the community’s…
Read More
July 29, 2022 in Announcements

RISC-V Global Summit Will Showcase Enormous Momentum for the Open Standard Hardware Architecture and Software Ecosystem | RISC-V International

 Call for Proposals, Sponsorship Sales, and Attendee Registration Now Open Event Spans December 12th through 15th; Summit Sessions Are December 13th and 14th    San Francisco – July 29, 2022…
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June 20, 2022 in Announcements, What's New

RISC-V Announces First New Specifications of 2022, Adding to 16 Ratified in 2021 | RISC-V International

Efficient Trace, Supervisor Binary Interface, Unified Extensible Firmware Interface, and Zmmul Multiply-Only Extension Accelerate Embedded- and Large-System Design. Six Additional Specifications Already In the Pipeline As Development Extends Into Vertical…
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