RISC-V Ecosystem News

FPGA System-on-Module for Power-Efficient Computation | Anis Zenadji, IEN Europe

The specialist in embedded services and products ARIES will present its brand-new System-on-Module (SoM) M100PFS at Embedded World 2020 (February 25 to 27, 2020 in Nuremberg. Stand 441 – hall 3A). The M100PFS SoM is based on the PolarFire® SoC, the System-on-Chip (SoC) FPGA family from Microchip that combines a high-performance 64-bit RISC-V multicore processor subsystem with low-power FPGA technology.article: https://www.ien.eu/article/fpga-system-on-module-for-power-efficient-computation/

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RVSoC Offers a Lightweight Linux-Capable RISC-V Core in Just 5,000 Lines of Verilog | Gareth Halfacree, Hackster.io

A team from the School of Computing at the Tokyo Institute of Technology have developed a portable and Linux-capable RISC-V system-on-chip (SoC) design in just 5,000 lines of Verilog — and pledges to release it to all.article: https://www.hackster.io/news/rvsoc-offers-a-lightweight-linux-capable-risc-v-core-in-just-5-000-lines-of-verilog-9a49976a6664

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Linux Kernel Continues Prepping for RISC-V’s Updated Supervisor Binary Interface | Michael Larabel, Phoronix

RISC-V’s Supervisor Binary Interface “SBI” is the interface between the platform-specific firmware and the running operating system or hypervisor for interacting with the supervisor execution environment in the higher privileged mode. The Linux kernel has been working to support a newer version of the SBI that is more extensible moving forward.article: https://www.phoronix.com/scan.php?page=news_item&px=RISC-V-Linux-SBI-v0.2-Continues

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Fast Access to Accelerators: Enabling Optimized Data Transfer with RISC-V | Shubu Mukherjee, Chief SoC Architect of SiFive

Domain-specific accelerators (DSAs) are becoming increasingly common in systems-on-chip (SoCs). A DSA provides higher performance per watt than a general-purpose processor by optimizing the specialized function it implements. Examples of DSAs include compression/decompression units, random number generators and network packet processors. A DSA is typically connected to the core complex using a standard IO interconnect, such as an AXI bus.article: https://www.sifive.com/blog/fast-access-to-accelerators-enabling-optimized-data-transfer-with-risc-v

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Can China Spawn Open Source Hardware Innovations Like Arduino and RISC-V? | Gu Zhengshu, EETimes China

Arduino, known for its open source microcontroller development board, released its latest development board for industrial IoT applications, Portenta H7, at CES this year. It uses MKR form factors, supports WiFi and Bluetooth wireless connections, and is equipped with a USB-C peripheral interface. . The core processor is STM32H747 from ST. This dual-core microprocessor integrates a Cortex-M7 core operating at 480MHz and a Cortex-M4 core operating at 240MHz. Based on…

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