Stay Connected With RISC-V
We send occasional news about RISC-V technical progress, news, and events.
One of the appealing things about open-source is that it invites modification to the underlying technology. In the case of the RISC-V instruction set architecture (ISA), this includes adding user-defined…
RISC-V Blog
One of the appealing things about open-source is that it invites modification to the underlying technology. In the case of the RISC-V instruction set architecture (ISA), this includes adding user-defined…
One of the main FOSSi projects I've been running the last couple of years is SweRVolf, a FuseSoC-based reference platform for Western Digital's family of RISC-V cores collectively called SweRV. I have…
Time is running out! The Call for Papers is open until Friday, September 10 at 11:59 pm PST. (Yes - TOMORROW!) Don't miss your opportunity to show off and share…
The Cryptography Extensions Task Group is delighted to announce the start of the public review period for the RISC-V Scalar Cryptography extensions. The RISC-V Scalar Cryptography extensions enable the acceleration…
In the News
PUFiot: An Essential Secure Coprocessor for RISC-V | Sam Chung, Sean H. Wu, and Evans Yang, PUF Security
The number of connected IoT devices exceeded 46 billion in 2021 and is expected to reach a remarkable 125 billion by 2030. This will shift the semiconductor market significantly as…
Read More
Video: It’s Not Just About Embedded! | The Yocto Project
“Embedded Linux people build custom Linux systems.” Thats how things are, right? And yeah, they do that a real lot for sure. But why invest all that effort? Aren’t there…
Read More
Zephyr RTOS + RISC-V – see the live demo at Open Source Summit/Embedded Linux Conference! | Jonathan Beri, Golioth
An Instruction Set Architecture (ISA) is like the DNA of a computer. It’s what makes Arm®-based processors Arm, x86-based CPUs Intel®, and so on. RISC-V is a free and open…
Read More
New release of SweRVolf RISC-V SoC project aims for lower barrier to entry | Gareth Halfacree, The Register
The SweRVolf project, a fully open system-on-chip designed as a reference platform for Western Digital's RISC-V SweRV cores, has announced a major new release promising lower barriers to entry for…
Read More
Announcements
RISC-V Launches the Open Hardware Diversity Alliance
Founded in Collaboration with the CHIPS Alliance, OpenPOWER Foundation, and Western Digital, the Alliance is Focused on Providing Support Programs, Learning Opportunities, and Mentoring for Women and Underrepresented Individuals in…
Read More
The 2021 RISC-V Summit Will Demonstrate Adoptions and Technical Advances This December in San Francisco
ZURICH and SAN FRANCISCO – July 28, 2021 – RISC-V International announced the 2021 RISC-V Summit that will bring together the open hardware community for three days of deep technical…
Read More