RISC-V Ecosystem News

Electronics Weekly Article: CEVA Buys Hillcrest Labs

RISC-V Foundation member, CEVA, bought Hillcrest labs which specializes in the fusion of data from multiple sensors to enable intelligent systems.Hillcrest Labs’ MotionEngine software supports a broad range of merchant sensor chips and is licensed to OEMs and semiconductor companies that can run the software on CEVA DSPs or a variety of RISC CPUs, including Arm Cortex-M and A-series and RISC-V based cores. To read more, please visit https://www.electronicsweekly.com/news/business/ceva-buys-hillcrest-labs-2019-07/.

Read More...

Sina Article: Chongqing Should Increase Its Voice In The Development Of New Generation Information Technology

At the Education, and Research Collaborative Innovation Exchange Conference held on July 20, Ni Guangnan, a well-known expert in China’s computer industry and academician, posed the question of “who can turn the traditional industry?” If the transformation and upgrading of the digital economy are coupled, any company can become a leader in this industry.In the future, RISC-V is likely to become one of the mainstream CPUs in the world. RISC-V…

Read More...

Leiphone Article: Bao Yungang, Institute Of Computing, Chinese Academy Of Sciences: There Is A “Dead Knot” In Open Source Chips, But This Is The Era Of Breaking The Knot | CCF-GAIR 2019

The fourth Global Artificial Intelligence and Robotics Summit (CCF-GAIR 2019) was officially held in Shenzhen. The summit was hosted by the China Computer Society (CCF), hosted by Lei Feng.com and the Chinese University of Hong Kong (Shenzhen), and co-organized by the Shenzhen Institute of Artificial Intelligence and Robotics.RISC-V was highlighted and broken down into the different aspects that it plays into on a platform and the benefits that open-source architecture…

Read More...

Elektronik Kalehti Article: Cheap Satellites With Open Source Architecture

The challenges posed by circuit board size, component numbers, power consumption, and heat generation are largely solved by the use of new radiation-resistant mixed-signal ICs based on the open RISC-V architecture.Utilizing a new open RISC-V ISA architecture, the FPGA circuitry can operate advantageously close to a remote measurement source. It enables autonomous data collection, condition monitoring, and load control at the payload source, thus freeing up resources from the satellite CPU…

Read More...

Phoronix Article: RISC-V’s Kernel Support Continues Maturing With Linux 5.3

In-step with more RISC-V hardware becoming available over time, the Linux kernel architecture support for RISC-V has continued maturing and with Linux 5.3 is in better shape.With the RISC-V support in Linux 5.3 there is now support for huge-pages, image header support (based on the ARM64 kernel image header), initial page table setup is split into two stages, CONFIG_SOC support has been started with initially catering to the SiFive SoCs, high-resolution timers…

Read More...

East Money Article: Huami Technology Joins RISC-V Foundation To Create Smart Wearable

Recently, Huami Technology officially joined the RISC-V Foundation and its large member base at the platinum level. As the world’s first wearable processor based on the RISC-V open-source architecture, the “Huangshan No. 1” was independently developed by Huami Technology and has been officially been put into mass production.Originally released in September 2018, the “Huangshan No. 1” processor greatly improved the AI ​​calculation efficiency by shifting it to the device side….

Read More...

Leiphone Article: Endurance, Ruisi, Science And Technology, Jianghang Intelligent Won The 2019 AI + Edge Computing Best Growth Award | CCF-GAIR 2019

On July 12 – 14, 2019, the 4th Global Artificial Intelligence and Robotics Summit (CCF-GAIR 2019) was officially held in Shenzhen, China. On the first day of the conference, after the “Artificial Intelligence Frontier” and “Artificial Intelligence Forty Years” commemorative sessions, the 2019 AI Best Growth Awards Ceremony was held at the CCF-GAIR 2019 dinner.The founding team of UC Berkeley’s original RISC-V was all in attendance. Most of these team members…

Read More...

Embedded Computing Design Article: Programmable RISC-V-Based AI Reference Camera Supports MicroPython, OpenMV

M5STACK has released the M5StickV K210 RISC-V AI camera, a programmable system that simplifies the integration of machine learning, image, and speech recognition through support for OpenMV and MicroPython programming.The 28 nm Kendryte K210 SoC at the heart of the camera leverages dual 64-bit RISC-V CPU cores running at 400 MHz, while the OmniVision OV7740 image sensor leverages OmniPixel3-HS technology. To read more, please visit https://www.embedded-computing.com/home-page/programmable-risc-v-based-ai-reference-camera-supports-micropython-openmv.

Read More...

IT Biz News Article: System Design Using RISC-V, Core Code Size Reduction

The instruction set (ISA) is open, so developers can design the chip by selecting only the core that they need, and it is advantageous for developers to implement the specialized functions required by various IoT applications.The RISC-V Foundation, in which many chip companies and internet service companies participate, is also actively moving. Starting with the 4th year since its inauguration, many reference designs will be released using core IP, which was…

Read More...

HelpNetSecurity Article: RISC-V Soft CPU Contest Challenges Designers To Develop A Hardware Secure RISC-V Soft CPU Solution

The RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), announced the call for submissions for the RISC-V Soft CPU Contest.The aim of the contest is to challenge designers to develop a hardware secure RISC-V soft CPU solution that can thwart malicious software security attacks. The contest is sponsored by RISC-V Foundation members Microchip…

Read More...