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We send occasional news about RISC-V technical progress, news, and events.
Efficient Trace, Supervisor Binary Interface, Unified Extensible Firmware Interface, and Zmmul Multiply-Only Extension Accelerate Embedded- and Large-System Design. Six Additional Specifications Already In the Pipeline As Development Extends Into Vertical…
RISC-V Blog
The RISC-V Developer Boards program drives RISC-V innovation by making development boards more accessible to the global RISC-V community. Read on to learn how the program now works and how…
Alibaba T-Head recently released a brand-new high-performance RISC-V SoC named the TH1520 at The RISC-V Summit China 2022. According to Alibaba “TH1520 demonstrates exceptional speed and power efficiency in an…
Recently at the RISC-V Summit China 2022 a new high-performance RISC-V-based chip platform named Wujian 600 and the TH1520 chip prototype was revealed. These products are compatible with the Linux-based…
Our Mi-V Ecosystem partner Emdalo Technologies Ltd. (Emdalo) has successfully customised PolarFire® SoC FPGA Linux® and associated boot flow for Skycorp Inc.’s recent space-mission on the International Space Station (ISS). …
In the News
ST to make European octacore RISC-V space chip with selectable cores | Nick Flaherty, EE News Europe
Space system designer CAES has built the first eight core fault tolerant chip that is selectable between different architectures, including RISC-V. The radiation hardened GR765 System-on-Chip (SoC) is the first user selectable…
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Arm vs RISC-V? Which One Is The Most Efficient? | Gary Explains
Arm has been making power efficient processors for decades. RISC-V is relativity new and many parts of its specifications aren't even ratified, but that hasn't stopped chip designers making RISC-V…
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Announcements
RISC-V Global Summit Will Showcase Enormous Momentum for the Open Source Hardware Architecture and Software Ecosystem | RISC-V International
Call for Proposals, Sponsorship Sales, and Attendee Registration Now Open Event Spans December 12th through 15th; Summit Sessions Are December 13th and 14th San Francisco – July 29, 2022…
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RISC-V Announces First New Specifications of 2022, Adding to 16 Ratified in 2021 | RISC-V International
Efficient Trace, Supervisor Binary Interface, Unified Extensible Firmware Interface, and Zmmul Multiply-Only Extension Accelerate Embedded- and Large-System Design. Six Additional Specifications Already In the Pipeline As Development Extends Into Vertical…
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Intel Corporation Makes Deep Investment in RISC-V Community to Accelerate Innovation in Open Computing
RISC-V welcomes Intel to the Board of Directors to collaborate on RISC-V IP and contribute engineering expertise to accelerate RISC-V software development ZURICH – February 7, 2022 – RISC-V International,…
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RISC-V Founding Member, Syntacore, Upgrades to Premier Level Membership
ZURICH – Dec. 7, 2021 – RISC-V International, a global open hardware standards organization, today announced that Syntacore, a semiconductor IP company specializing in customizable microprocessor cores and tools based on…
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