What’s New

RISC-V International and seL4 Foundation Announce New Security Milestone

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SAN FRANCISCO, May 5, 2021 – Today, the seL4 Foundation and RISC-V International announced that the verified seL4 microkernel on the RV64 architecture has been proved down to the executable…

RISC-V Blog

seL4 on RISC-V Verified to Binary Code

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Author: Gernot Heiser, seL4 FoundationIn June 2020 we announced that the seL4 microkernel, the world’s first operating system (OS) kernel with a machine-checked proof of implementation correctness, has now also…

The world’s first DSP based on RISC-V ISA is about to be mass-produced

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RISC-V, the "youngest" ISA (Instruction Set Architecture), which was born in year 2010, has attracted many giant supporters, such as Google, Qualcomm, Western Digital, Alibaba, Huawei, and UNISOC. In recent…

RISC-V Developer Boards to drive innovation

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We are at an incredible inflection point for RISC-V. We are making history and we want you to be a part of it! RISC-V is now being engineered into everything…

Bugs: A verification engineer’s dream, a designer’s nightmare

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This blog was originally published on the Axiomise website. Read the original blog. Who wants to have bug escapes? Nobody. Who wants to have bugs in the design? Nobody. Who…

In the News

May 5, 2021 in In the News

Video: (EN) Accelerating RISC V AI and IoT Development with Andes Software Solutions | Andes Technology

2021 Andes RISC-V CON Webinar Date: April 28, 2021 Topic: Accelerating RISC V AI and IoT Development with Andes Software Solutions Speaker: Simon Wang, Technical Marketing Manager, Andes Technology AI…
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May 4, 2021 in In the News

Video: aicas and SiFive Demo on RISC-V Board

aicas and SiFive Bridge Flexibility and Performance with RISC-V, JamaicaVM Integration aicas GmbH and SiFive, Inc are enabling embedded systems developers to close the gaps between the freedom of open…
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May 4, 2021 in In the News

Video: The RISC-V Online Tutor | British Computer Society Open Source Specialists

Presented Fearghal Morgan, NUI Galway, Ireland RISC-V Online Tutor provides structured, self-paced RISC-V architecture and applications training and reference. It uses the vicilogic platform (online learning, remote FPGA prototyping and…
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May 2, 2021 in In the News

Video: MPU6050 Gyro + Accelerometer Sensor Demo using VEGA Processor [ RISC-V ISA]

Demonstrating MPU6050 Gyro + Accelerometer Sensor using VEGA Microprocessor based on RISC-V ISA
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Announcements

May 5, 2021 in Announcements, What's New

RISC-V International and seL4 Foundation Announce New Security Milestone

SAN FRANCISCO, May 5, 2021 – Today, the seL4 Foundation and RISC-V International announced that the verified seL4 microkernel on the RV64 architecture has been proved down to the executable…
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April 29, 2021 in Announcements

RISC-V International Welcomes Chengwei Capital as a Premier Member

Investment firm Chengwei Capital to join the RISC-V Board of Directors and Technical Steering Committee Zurich – April 29, 2021 – RISC-V International, a non-profit corporation controlled by its members…
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March 24, 2021 in Announcements

CHIPS Alliance and RISC-V International Invite the RISC-V Community to Participate in Updating a New Unified Memory Architecture Standard

New joint working group will enhance the OmniXtend Cache Coherency architecture SAN FRANCISCO, March 24, 2020 – RISC-V International, a non-profit corporation controlled by its members to drive the adoption…
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March 2, 2021 in Announcements

Learn About the RISC-V ISA with Two Free Training Courses from The Linux Foundation and RISC-V International

The online courses are offered on edX.org and will make RISC-V training more accessible SAN FRANCISCO - EMBEDDED WORLD - March 2, 2021 – The Linux Foundation, the non-profit organization…
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