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We send occasional news about RISC-V technical progress, news, and events.
2nd RISC-V Summit in China will be broadcast online with 12 concurrent in-person events in leading technology cities throughout the country; 100,000 online viewers expected Global summit includes keynotes, tutorials,…
RISC-V Blog
2nd RISC-V Summit in China will be broadcast online with 12 concurrent in-person events in leading technology cities throughout the country; 100,000 online viewers expected Global summit includes keynotes, tutorials,…
How Secure is Your Software? It’s a simple question with—perhaps all too often—a complex answer. A more telling question may be: just how quickly can your software be breached? Hosting…
Welcome to Our New Elected RISC-V Board Members By Calista Redmond, CEO RISC-V International, August 1, 2022 We are honored to share the results of our 2022 Board of Directors…
Recent rapid development of various applications represented by Deep Learning (DL) calls for a much-needed increase in established chip matrix computing capability. Therefore, CPU manufacturers strive to better support matrix…
In the News
Imperas leads the RISC-V verification ecosystem as the first to release an open-source SystemVerilog RISC-V processor functional coverage library | Imperas Software
Complete source file access allows easy adoption and enables user extensions for advanced microarchitecture verification that helps all RISC-V projects accelerate time-to-market goals. Imperas Software Ltd., the leader in RISC-V simulation…
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Andes Technology RISC-V Processors Reveal Outstanding Performance and Efficiency in MLPerf Tiny | Andes Technology
Andes Technology Corporation (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, submits MLPerf Tiny v0.7 benchmark…
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DAC 2022 – Is it too risky not to adopt RISC-V? | Brett Cline, Codasip
I was fortunate enough to attend the 59th Design Automation Conference (DAC) in San Francisco last week. Aside from the Covid closure in 2020 I’ve been going to DAC since…
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RISC-V Standardizes E-Trace and Binary Interface | William G. Wong, Electronic Design
RISC-V International has released a number of new specifications that enhance the RISC-V ecosystems. I talked with Chief Technology Officer for RISC-V International, Mark Himelstein, about their latest specifications. This includes E-Trace, the…
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Announcements
RISC-V Global Summit Will Showcase Enormous Momentum for the Open Source Hardware Architecture and Software Ecosystem | RISC-V International
Call for Proposals, Sponsorship Sales, and Attendee Registration Now Open Event Spans December 12th through 15th; Summit Sessions Are December 13th and 14th San Francisco – July 29, 2022…
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RISC-V Announces First New Specifications of 2022, Adding to 16 Ratified in 2021 | RISC-V International
Efficient Trace, Supervisor Binary Interface, Unified Extensible Firmware Interface, and Zmmul Multiply-Only Extension Accelerate Embedded- and Large-System Design. Six Additional Specifications Already In the Pipeline As Development Extends Into Vertical…
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Intel Corporation Makes Deep Investment in RISC-V Community to Accelerate Innovation in Open Computing
RISC-V welcomes Intel to the Board of Directors to collaborate on RISC-V IP and contribute engineering expertise to accelerate RISC-V software development ZURICH – February 7, 2022 – RISC-V International,…
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RISC-V Founding Member, Syntacore, Upgrades to Premier Level Membership
ZURICH – Dec. 7, 2021 – RISC-V International, a global open hardware standards organization, today announced that Syntacore, a semiconductor IP company specializing in customizable microprocessor cores and tools based on…
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