RISC-V Ecosystem News

Nicholas Charbonnier, commonly known as “Charbax,” interviewed RISC-V Foundation Executive Director Rick O’Connor, as well as co-exhibiting members GreenWaves Technologies, UltraSoC and VectorBlox at the RISC-V Foundation booth at Embedded World 2018. The video also includes short product demonstrations from VP of Business Development at GreenWaves Technologies Martin Croome, CEO at VectorBlox Guy Lemieux and VP of Sales at UltraSoC John MacDermott. To watch the full video, please visit: https://www.youtube.com/watch?v=i7X0gBo_4UU&t=311s.

Bluespec Inc. has released Piccolo, its first in a family of RISC-V open-source processors provided as a vehicle for open innovation in embedded systems. Piccolo is a 3-stage RV32IM processor whose small “footprint” is ideal for many IoT applications. The repository (https://github.com/bluespec/Piccolo) contains a royalty-free synthesizable Verilog core that can be easily integrated and deployed into an ASIC or FPGA. Bluespec, Inc. will actively maintain Piccolo. It also offers commercial-grade…

The Linux Foundation, the nonprofit organization enabling mass innovation through open source, today announced the session agenda for Open Source Summit Europe and Embedded Linux Conference + OpenIoT Summit Europe, taking place October 22-24 in Edinburgh, Scotland.Embedded Linux Conference + OpenIoT Summit Europe session highlights include: Pushing Kubernetes Experience to IoT Devices – Erno Aapa, Eliot Common Attacks on IoT Devices – Christina Quast Embedded Linux on RISC-V Architecture – Status Report – Khem Raj, Comcast Supporting Hardware…

UltraSoC today announced that it has appointed MosChip as its technical sales representative in India, as part of a program to support the rapidly developing global market for its embedded analytics technology.UltraSoC recently supported the first RISC-V Workshop in Chennai, which included sessions demonstrating how RISC-V can be a game-changer for India’s semiconductor industry. A clear message from the event was that engineers are likely to initially deploy RISC-V alongside other cores; requiring a…

Antmicro, a software-driven technology vendor for edge AI and cyber-physical systems, and SiFive, the first fabless semiconductor company to offer customized silicon based on the free and open RISC-V Instruction Set Architecture, are announcing a milestone partnership to bring forth a complete offering for early adopters of RISC-V.The two RISC-V Platinum Founding Members together provide competitive advantage for their common customers. SiFive’s world-first, Linux-enabled RISC-V development board, the HiFive Unleashed, and the earlier HiFive1 development kit…

In this article, Frank K Gürkaynak of ETH Zurich explores and explains his team’s process of choosing and utilizing the open-source hardware platform RISC-V in an academic environment.Five years ago we started the Parallel Ultra Low Power (PULP) project at ETH Zürich together with the University of Bologna under the leadership of Luca Benini. Our goal was to explore novel computing architectures that are able to get the most out…

Andes Technology Corporation, the leading supplier of high performance, low-power and small embedded CPU cores, has created a RISC-V core licensing project and has signed joint promotion agreements to form a multinational design service alliance with several top ASIC/SoC design service companies. The alliance is expected to continue expanding eventually reaching 20 or more companies globally in the following several months. Now the alliance in alphabetical order includes ASIC Land in Korea, SiEn…

QuickLogic Corporation, a developer of ultra-low power embedded FPGA IP and programmable logic solutions, today announced that the ETH Zurich, [in German: Eidgenössische Technische Hochschule Zürich (ETH)], a renowned technical university located in Zurich, Switzerland, will collaborate to integrate QuickLogic’s ArcticPro embedded FPGA (eFPGA) technology onto the university’s PULP platform. ETH chose QuickLogic’s technology for its ultra-low power operation and its ability to create new options for extremely power efficient hardware/software implementations.ETH is a science, technology,…

The RISC-V open instruction set architecture (ISA) has scored another pair of big wins this week, with SiFive‘s core intellectual property (IP) being picked for a pair of high-performance solid-state drive (SSD) families from Mobiveil and Fadu.Designed to scale from low-power single-core microcontroller implementations to high-performance many-core supercomputers, the RISC-V ISA began life in 2010 at the University of California at Berkeley as a collaborative alternative to proprietary ISAs including…

 SiFive, the leading provider of commercial RISC-V processor IP, and FADU, a fabless company developing solutions and systems for the memory and storage market, today announced the availability of FADU’s Annapurna SSD Controller and FADU Bravo Series Enterprise SSD, powered by SiFive’s industry leading 64-bit, E51 multicore RISC-V Core IP.The FADU Annapurna SSD controller is the world’s first RISC-V based SSD Controller and provides the highest throughput (3.5GB) and IOPS…