In the News

Previously I talked about my excitement for RISC-V, with one of my goals to see if I can get a decentralised stack running on top of it. My first project...

The De-risc project has shown the first milestones for a purely European multicore RISC-V processor for satellite, space and HAPS designs. Read the full article.

In my last post I talked about my excitement for RISC-V. Since then I have been experimenting to see what I can do before getting my hands on real hardware....

Given the recent developments around RISC-V (pronounced "risk-five"), a free and open-source instruction set architecture, and my interest in open hardware, coupled with the fact that for RKern starting small...

Talk of configuring a base processor or adding custom extensions to resolve hardware-software design tradeoffs in a system on chip (SoC) is not new. This has been a key part...

“De-RISC, the Horizon 2020 project (EIC-FTI 869945) that aims to create a market-ready platform based on RISC-V for the aerospace market, celebrates its one-year anniversary." After one year of execution, De-RISC continues...

CORE-V CVA6 is a RISC-V CPU that can boot an embedded Linux image. RISC-V is an open source, extensible Instruction Set Architecture (ISA) that has gained a lot of popularity...

I have been following RISC-V for many years, and I am enamoured with the goal of open source chip ISA & hardware. However last week they announced a new dev...

Alibaba’s T-head subsidiary amd Allwinner have produced a single-core, RISC-V-based XuanTie C906 processor with MMU that will appear on a sandwich-style, Linux-driven, $12.50 Sipeed SBC due in two months. Read...