RISC-V Ecosystem News

Antmicro And SiFive Join Forces To Propose Complete RISC-V Offering

Antmicro, a software-driven technology vendor for edge AI and cyber-physical systems, and SiFive, the first fabless semiconductor company to offer customized silicon based on the free and open RISC-V Instruction Set Architecture, are announcing a milestone partnership to bring forth a complete offering for early adopters of RISC-V.The two RISC-V Platinum Founding Members together provide competitive advantage for their common customers. SiFive’s world-first, Linux-enabled RISC-V development board, the HiFive Unleashed, and the earlier HiFive1 development kit…

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All About Circuits Article: Utilizing Open Source Hardware in Academic Environments

In this article, Frank K Gürkaynak of ETH Zurich explores and explains his team’s process of choosing and utilizing the open-source hardware platform RISC-V in an academic environment.Five years ago we started the Parallel Ultra Low Power (PULP) project at ETH Zürich together with the University of Bologna under the leadership of Luca Benini. Our goal was to explore novel computing architectures that are able to get the most out…

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Andes Technology Forms A Multinational Alliance With ASIC Design Service Companies To Provide RISC-V Total Solutions

Andes Technology Corporation, the leading supplier of high performance, low-power and small embedded CPU cores, has created a RISC-V core licensing project and has signed joint promotion agreements to form a multinational design service alliance with several top ASIC/SoC design service companies. The alliance is expected to continue expanding eventually reaching 20 or more companies globally in the following several months. Now the alliance in alphabetical order includes ASIC Land in Korea, SiEn…

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QuickLogic Collaborates With ETH Zurich To Integrate eFPGA Into PULP Platform

QuickLogic Corporation, a developer of ultra-low power embedded FPGA IP and programmable logic solutions, today announced that the ETH Zurich, [in German: Eidgenössische Technische Hochschule Zürich (ETH)], a renowned technical university located in Zurich, Switzerland, will collaborate to integrate QuickLogic’s ArcticPro embedded FPGA (eFPGA) technology onto the university’s PULP platform. ETH chose QuickLogic’s technology for its ultra-low power operation and its ability to create new options for extremely power efficient hardware/software implementations.ETH is a science, technology,…

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Bit-tech Article: SiFive’s RISC-V Cores Launch In Two SSD Families

The RISC-V open instruction set architecture (ISA) has scored another pair of big wins this week, with SiFive‘s core intellectual property (IP) being picked for a pair of high-performance solid-state drive (SSD) families from Mobiveil and Fadu.Designed to scale from low-power single-core microcontroller implementations to high-performance many-core supercomputers, the RISC-V ISA began life in 2010 at the University of California at Berkeley as a collaborative alternative to proprietary ISAs including…

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FADU Launches Industry Leading SSD Solutions Powered By SiFive RISC-V Core IP

 SiFive, the leading provider of commercial RISC-V processor IP, and FADU, a fabless company developing solutions and systems for the memory and storage market, today announced the availability of FADU’s Annapurna SSD Controller and FADU Bravo Series Enterprise SSD, powered by SiFive’s industry leading 64-bit, E51 multicore RISC-V Core IP.The FADU Annapurna SSD controller is the world’s first RISC-V based SSD Controller and provides the highest throughput (3.5GB) and IOPS…

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eSilicon Licenses Industry-Leading SiFive E2 Core IP For Next-Generation SerDes IP

SiFive, the leading provider of commercial RISC-V processor IP, and eSilicon, an independent provider of FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, today announced that, after extensive review and testing of available options in the market, eSilicon has selected the SiFive E2 Core IP Series as the best solution for its next-generation SerDes IP at 7nm.eSilicon’s 7nm SerDes IP represents a new breed of performance and versatility based on…

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Mobiveil Inc. And SiFive Partner To Develop RISC-V Based Configurable SSD Platform For Data Center And Enterprise Storage Applications

Mobiveil, Inc. a provider of Serial Interconnect IP blocks and platforms targeting Flash Storage, IoT and Communication markets, has selected SiFive’s multicore E51 and U54 Core IPs to power Mobiveil’s new advanced configurable Gen4 PCIe-NVMe SSD platform offering a high performance and low power SSD solution for data center storage applications. SiFive’s heterogenous, coherent RISC-V core complex in a high-performance FPGA along with Mobiveil’s Silicon Proven IP blocks (Gen4 PCIe,…

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TechNode Article: Lack Of Support For Young Researchers Is Holding Back China’s Innovation

On June 30, computer instruction set architecture (ISA) RISC-V’s official tech promotion RISC-V Foundation had its only 2018 conference for Mainland China at Fudan University, Shanghai. Exclusive for professionals and high-level investors, the foundation’s conference showed some of the latest ISA technologies including the world’s smallest drone developed by European scientists.Not long after the conference, RISC-V technology received official government support. The Shanghai Municipal Commission of Economy and Information released a…

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EE Times Article: India Startup Preps RISC-V, AI Cores

A startup in India announced ambitious plans to design and license RISC-V-based processor cores as well as deep-learning accelerators and SoC design tools. InCore Semiconductors will make its first cores available before the end of the year.The effort marks a small but significant addition to the RISC-V ecosystem. It shows that the initiative is gaining global interest for its open-source instruction set architecture as an alternative to offerings from Arm and…

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