RISC-V Ecosystem News

Design News Article: Linux Now Has its First Open Source RISC-V Processor

With its new, first-of-its-kind Linux-compatible multi-core CPU, SiFive is moving to pushing the open source RISC-V architecture into an expanded world of use cases, including machine learning and IoT.SiFive has declared that 2018 will be the year of RISC V Linux processors.When it released its first open-source system on a chip, the Freeform Everywhere 310, last year, Silicon Valley startup SiFive was aiming to push the RISC-V (“risk five”) architecture to transform…

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RISC-V Ecosystem to Present at 15th International System-on-Chip (SoC) Conference, Exhibit & Workshops

Six Companies from the RISC-V Ecosystem to Host Speaking Sessions at Conference WHERE:The 15th International System-on-Chip (SoC) Conference, Exhibit & Workshops, University of California, Irvine (UCI) , Irvine, Calif., 92697, Calit2 Building 2 WHEN:Wednesday, Oct. 18 to Thursday, Oct. 19, 2017 WHAT:The RISC-V Foundation will feature six member organizations at this year’s International SoC Conference. Ted Speers, VP and Head of Product Architecture and Planning for Microsemi SoC Group, a…

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RISC-V Ecosystem to Showcase New Implementations of RISC-V ISA at Linley Processor Conference 2017

RISC-V Members Including Codasip, Dover Microsystems, Imperas, Microsemi and SiFive to Demo New Innovative Products Based on Open, Free RISC-V ISA WHERE:Linley Processor Conference 2017, Hyatt Regency Santa Clara, 5101 Great America Pkwy, Santa Clara, Calif., 95054 WHEN:Wednesday, Oct. 4 to Thursday, Oct. 5, 2017 WHAT:The RISC-V Foundation, together with members including Codasip, Dover Microsystems, Imperas, Microsemi and SiFive, will exhibit new RISC-V implementations at the Linley Processor Conference 2017….

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7th RISC-V Workshop Registration

7th RISC-V Workshop November 28-30, 2017Registration for the 7th RISC-V Workshop, hosted by Western Digital in Milpitas California on November 28-30, 2017 is now open.  As with past workshops, our goals for these events are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build consensus on the future evolution of the instruction set. This will be…

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RISC-V Foundation to Showcase Growth of New Architecture at Hot Chips 29

Foundation members demo RISC-V-based implementations WHEREHot Chips 29, Flint Center for the Performing Arts, 21250 Stevens Creek Blvd, Cupertino, Calif., 95014 WHENSunday, Aug. 20 to Tuesday, Aug. 22, 2017 WHATRISC-V® Foundation will exhibit at Hot Chips 29, showcasing the momentum of its Instruction Set Architecture (ISA), the industry’s first open, free architecture. RISC-V founding member, SiFive, will host a session detailing the industry’s first open-source RISC-V system-on-chip (SoC). Representatives from…

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RISC-V E-Newsletter June 2017

Click HERE to Join the RISC-V Foundation Mail Lists First RISC-V Foundation workshop outside North America sells out The 6th RISC-V Workshop, co-hosted by NVIDIA and the Shanghai Jiao Tong University (SJTU) was held in Shanghai China on May 8-11, 2017.  This was our first RISC-V Foundation workshop held outside of North America and as with past workshops, this event was sold out with over 270 registered attendees. Workshop proceedings are…

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7th RISC-V Workshop Call for Papers

Call for Papers 7th RISC-V Workshop November 28-30, 2017We’re seeking proposals for talks and poster presentations conveying recent activity in the RISC-V community at the upcoming 7th RISC-V workshop hosted by Western Digital in Milpitas California on November 28-30, 2017.Talks can be of two lengths (25 minutes and 12 minutes), and talk presenters are expected to also participate in the poster session to allow extended discussion. All poster presenters will give…

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7th RISC-V Workshop Save the Date

7th RISC-V Workshop November 28-30, 2017Please save the date and plan to join us for our 7th RISC-V Workshop, hosted by Western Digital in Milpitas California November 28-30, 2017.  As with past workshops, our goals for these events are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build consensus on the future evolution of the instruction set.Each of our past…

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The RISC-V Memory Consistency Model

Krste Asanović, Chairman, RISC-V FoundationMemory consistency models (MCMs) are known to flummox even experienced computer architects, so it is perhaps not surprising that recent news articles had some difficulty portraying the nuances behind recent findings by a team of Princeton researchers led by Professor Margaret Martonosi.  The RISC-V Foundation is publishing this article to help the RISC-V community understand the deeper implications of the Princeton study. Executive Summary The Princeton team…

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RISC-V Enters Mainstream at Embedded World 2017

Berkeley, California – Over the last year the RISC-V architecture has evolved from an academic research interest to a mainstream embedded processor technology with a rich ecosystem and a fast-growing number of real-world implementations. As a sign of this progress, a number of companies will be demonstrating commercial implementations of RISC-V products next week at Embedded World 2017, the leading international trade fair for embedded systems (March 14-16, Nuremberg, Germany) https://www.embedded-world.de/enRISC-V…

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