RISC-V Ecosystem News

Electronic Design Article: Hard-Core RISC-V Cores Mate With FPGA

By integrating hard-core RISC-V CPUs with its latest FPGAs, Microsemi, a Microchip company, has further bolstered its RISC-V support. This is the same approach that Intel/Altera and Xilinx have done with Arm cores and their system-on-chip (SoC) FPGA offerings. Microsemi also has an FPGA with a hard-core ARM Cortex-M3, but its Mi-V initiative has been pushing soft-core RISC-V support in its FPGA lines.Microsemi’s 64-bit RISC-V SoC FPGA is based on its PolarFire FPGA. The approach…

Read More...

Codasip Releases Studio 8, A Breakthrough In RISC-V Automation, And The Bk7 RISC-V Processor Core For Real-Time Computing Applications

CodasipGmbH, the leading supplier of RISC-V embedded processor IP, announced today the latest version of Studio, a suite of tools optimized for the development and verification of RISC-V processors, and the Bk7 processor, the first Codasip RISC-V core optimized for Linux and real-time performance.“As the RISC-V ISA specification evolves and adds an ever-increasing number of optional architecture extensions, a processor design methodology that allows for both rapid architectural exploration and simplified creation of easily implementable RTL…

Read More...

EE World Article: CPU Cores With RISC-V Technology Now Support The Custom Extension

Andes Technology announced its newly-released AndeStar V5 CPU cores – N25/N25F, NX25/NX25F, A25 and AX25 – support the Andes Custom Extension (ACE) feature. The AndeStar V5 architecture is the result of RISC-V technology incorporated with Andes innovations based on rich experience in serving embedded processor IPs for over 10 years. The ACE feature enables embedded designers to add customized instructions on their Andes V5 CPU cores with ease.RISC-V is an…

Read More...

EE World Article: Design Verification Platform For RISC-V-Based AI And ML Semiconductor Solutions

Valtrix Technologies, an EDA company delivering Design Verification (DV) solutions for the semiconductor industry, announced that Esperanto Technologies has selected Valtrix’s STING DV Platform for design verification of its energy-efficient semiconductor solutions for artificial intelligence (AI) and machine learning (ML) based on the open standard RISC-V instruction set architecture. Esperanto plans to use STING for verifying the architectural compliance and functional correctness of its 7nm AI Supercomputer-on-Chip based on the high-performance ET-Maxion…

Read More...

*Andes Custom Extension™ Further Accelerates Your High Performance RISC-V Processors

Andes Technology today announced its newly-released AndeStar™ V5 CPU cores – N25/N25F, NX25/NX25F, A25 and AX25 – support the Andes Custom Extension™ (ACE) feature. The AndeStar™ V5 architecture is the result of RISC-V technology incorporated with Andes innovations based on rich experience in serving embedded processor IPs for over 10 years. The ACE feature enables embedded designers to add customized instructions on their Andes V5 CPU cores with ease.RISC-V is…

Read More...

Renode 1.6 Released Making Linux-Enabled RISC-V Microchip PolarFire SoC Available To Everyone

Antmicro, a high-tech company focusing on introducing open technologies to modern edge computing systems and RISC-V ecosystem leader, has announced today adding support for the groundbreaking Linux-enabled PolarFire SoC revealed earlier by Microchip Technology in the revolutionary open source Renode software development framework. The announcement comes during the inaugural RISC-V Summit currently taking place in Santa Clara, California.Microchip PolarFire SoC is a new class of SoC FPGAs that combines the industry’s lowest power mid-range…

Read More...

ABOpen Article: Western Digital Unveils Open SweRV RISC-V Core

Western Digital has unveiled its first in-house RISC-V core, dubbed SweRV, and it has confirmed plans to release it under an open source license early next year.Part of a company initiative, started in 2017, to switch from proprietary instruction set architectures (ISAs) to the open RISC-V ISA across its storage processing products, Western Digital’s SweRV marks the company’s first public announcement of an in-house processing core. Based on the 32-bit…

Read More...

Linus Tech Tips Video: Design Your Own CPU!!!

In a video sponsored by SiFive, Yvonne Ho from Linus Tech Tips describes the RISC-V architecture and demonstrates SiFive technology using the RISC-V ISA. Check out SiFive’s core designer here: https://www.sifive.com/core-designer. To watch the video, please visit: https://www.youtube.com/watch?v=jNnCok1H3-g&feature=youtu.be.

Read More...

AnandTech Article: Western Digital Reveals SweRV RISC-V Core, Cache Coherency Over Ethernet Initiative

Western Digital this week made three important announcements concerning its RISC-V-based processor initiative launched last year. The company introduced its own SweRV general-purpose core, its OmniXtend cache coherency over Ethernet technology, and the open-sourced SweRV Instruction Set Simulator (ISS). Western Digital expects that the hardware and software will be used for various solutions aimed at Big Data and Fast Data applications, including flash controllers and SSDs.Western Digital’s RISC-V SweRV core is a…

Read More...

Tom’s Hardware Article: Western Digital Bets Big On RISC-V With Own Processor, Other Innovations

At the RISC-V Summit, Western Digital (WD) announced three open-source innovations related to the RISC-V instruction set architecture (ISA): a new open source RISC-V CPU core, an open standard initiative for cache coherent memory over a network, and an open source RISC-V instruction set simulator.WD announced that it has built its own RISC-V core, which it calls “SweRV,” and that it intends to open source it. The CPU core features…

Read More...