TestRIG (Testing with Random Instruction Generation) is a testing framework for RISC-V implementations. The RISC-V community has standardized a formal model of the architecture in the Sail language, giving a…
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Introduction Following the gap analysis done in the second half of 2023, the Vector Special Interest Group (SIG-Vector) has been working on specifying instructions to accelerate matrix operations. Two Task…
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Tammo Mürmann has just commenced his PhD studies at the Technical University of Darmstadt as part of the Embedded Systems and Applications Group (ESA). During his studies, he already participated…
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RISC-V – never heard of it? The open-source processor architecture is relatively new, but already making big waves as the ISA for all sorts of applications. In this talk media.ccc.de…
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