RISC-V Workshop in Barcelona Proceedings

RISC-V Workshop in Barcelona Proceedings

7-10 May, 2018

Co-hosted By

Co-sponsored By

 
Keynote sessions at the event included Robert Oshana, vice president of software engineering research and development at NXP, Martin Fink, executive vice president and chief technology officer at Western Digital, and Mateo Valero, director at the Barcelona Supercomputing Center.

• Monday, May 7, 2018 – A half-day of tutorials from the working groups of the RISC-V technical committee. The sessions covered topics such as base ISA ratification, BitManip, compliance, debug, formal spec, memory model, opcode space management, privilege spec, security, software toolchain and vector extensions.
• Tuesday and Wednesday, May 8-9, 2018 – Two full days of presentations on RISC-V architecture, commercial and open-source implementations, software and silicon, vectors and security, applications and accelerators, simulation infrastructure and more.
• Thursday, May 10, 2018 – The event will conclude with RISC-V Foundation meetings, restricted to members of the RISC-V Foundation. The day will consist of Technical and Marketing Committee face-to-face meetings to progress the work currently underway within our various Task Groups.

Each workshop has helped both document the rapidly rising popularity of RISC-V and boosted it further due to the information shared and collaborations formed at the event.
For additional photos from the event, please visit: http://www.shingarov.com/riscv/.

Proceedings

Check out the slides and videos from each of the sessions below.

Monday, 7 May, 2018 RISC-V Workshop Tutorial Day

| Video

Tuesday, 8 May, 2018 RISC-V Workshop Day 1

Wednesday, 9 May, 2018 RISC-V Workshop Day 2