RISC-V Foundation at Design Automation Conference (DAC) Proceedings
June 24 – 27, 2018
The 54th Design Automation Conference (DAC) was held at the Moscone Center West, in San Francisco from June 25 – 25, 2018. DAC 2018 demonstrated the exciting momentum of the RISC-V ecosystem. The RISC-V Foundation booth featured member companies Imperas Software, Microsemi, SiFive, Syntacore, UltraSoC and Western Digital. Throughout the event, the RISC-V Foundation hosted panels and speaking sessions, held a scavenger hunt and hosted networking happy hours.
DAC invited the Foundation to present the RISC-V Ecosystem – Reshaping the CPU Landscape workshop on how the free and open RISC-V ISA is creating a paradigm shift in industry, reinvigorating semiconductor design and reshaping traditional business models. The workshop featured sessions from RISC-V Foundation Executive Director Rick O’Connor, Markus Levy and Alex Badicioiu at NXP, and Palmer Dabbelt at SiFive.
Rick O’Connor at the RISC-V Foundation also participated in the panel Core Choices: How To Navigate The Brave New World Of IP, which was hosted by Junko Yoshida at EE Times. David Patterson, vice chair of the RISC-V Foundation’s Board of Directors, presented his keynote A New Golden Age For Computer Architecture: Domain Specific Accelerators and Open RISC-V to DAC attendees. Other sessions at DAC also featured members of the RISC-V ecosystem including Krste Asonvic at SiFive, and Abbas Rehimi, Davide Rossi and Luca Benini at ETH Zurich.
Ecosystem News
- Inside Secure And Andes Join Forces To Deliver Secure IoT Solutions To Chipmakers For Greater China And Asia Markets
- SiFive Unveils E2 Core IP Series For Smallest, Lowest Power RISC-V Designs
Coverage Highlights
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- All About Circuits: RISC-V: Opening a New Era of Innovation for Embedded Design
- Design & Reuse: Inside Secure and Andes join forces to deliver secure IoT solutions to chipmakers for greater China and Asia markets
- Design & Reuse: SiFive Unveils E2 Core IP Series for Smallest, Lowest Power RISC-V Designs
- Hackday: SiFive Releases Smaller, Lower Power RISC-V Cores
- ReadITQuik: Inside Secure & Andes Partner to Provide Advanced Security Capabilities to Chipmakers for IoT, Cloud Connectivity
- Semiconductor Engineering: Wednesday At DAC 2018
- VentureBeat: SiFive Claims Its New Open Chip Cores Can Beat ARM’s Power-efficient Processors
Proceedings
Check out slides from some of the sessions below and stay tuned for the videos.
Sunday, June 24, 2018
| Time | Session | Speaker, Affiliation | Slides |
| 1:00pm | RISC-V ISA & Foundation Overview | Rick O’Connor, RISC-V Foundation | Slides |
| RISC-V – A Diversity of Core and Accelerator Choices | Markus Levy, NXP | Slides | |
| RISC-V OS Landscape | Palmer Dabbelt, SiFive | Slides | |
| Designing a Custom RISC-V Core Using Chisel | Alex Badicioiu, NXP | Slides | |
| 4:00pm | Wrap Up |
Monday, June 25, 2018
| Time | Session | Speaker, Affiliation | Slides |
| 11:00am | RISC-V ISA & Foundation Overview | Rick O’Connor, RISC-V Foundation | Slides |
| 12:00pm | Introducing The Latest RISC-V Core IP Series | Drew Barbier, SiFive | Slides |
| 1:00pm | Panel: Meet The RISC-V Members at DAC 2018 | ||
| 2:00pm | Fueling The RISC-V Ecosystem with Microsemi’s Mi-V Programmable Solutions | Ted Marena, Microsemi | Slides |
| 3:00pm | Machine Learning with RISC-V | Filip Blagojevic, Western Digital | Slides |
| 4:00pm | It’s Not Just The Core, It’s The System: Processor Trace In A Holistic World | Randy Fish, UltraSoc | Slides |
| 4:30pm | RISC-V Virtual Platforms, Simulators and Software Tools | Simon Davidmann, Imperas Software | Slides |
| 5:00pm | RISC-V: Enabling Innovation In Embedded and Enterprise Data-Centric Computing Architectures; Networking Event and Daily Prize Draw | Zvonimir Bandic, Western Digital | Slides |
Tuesday, June 26, 2018
| Time | Session | Speaker, Affiliation | Slides |
| 11:00am | RISC-V ISA & Foundation Overview | Rick O’Connor, RISC-V Foundation | Slides |
| 12:00pm | It’s Not Just The Core, It’s The System: Processor Trace In A Holistic World | Randy Fish, UltraSoc | Slides |
| 1:00pm | Panel: The Key Role for the Commercial Software Tools Ecosystem for RISC-V | ||
| 2:00pm | RISC-V Support for Persistent Memory Systems | Matheus Ogleari, Western Digital | Slides |
| 3:00pm | RISC-V Virtual Platforms, Simulators and Software Tools | Simon Davidmann, Imperas Software | Slides |
| 4:00pm | Introducing The Latest RISC-V Core IP Series | Drew Barbier, SiFive | Slides |
| 4:30pm | SCRx Family of The RISC-V Compatible Processor IP | Alexander Redkin, Syntacore | Slides |
| 5:00pm | Keynote on Vision and History of RISC-V; Networking Event and Daily Prize Draw | Yunsup Lee and Ali Sana, SiFive | Slides |
Wednesday, June 27, 2018
| Time | Session | Speaker, Affiliation | Slides |
| 11:00am | Fueling The RISC-V Ecosystem with Microsemi’s Mi-V Programmable Solutions | Ted Marena, Microsemi | Slides |
| 12:00pm | SCRx family of The RISC-V Compatible Processor IP | Alexander Redkin, Syntacore | Slides |
| 1:00pm | Panel: New Markets & Applications for RISC-V | ||
| 2:00pm | Panel: Meet The RISC-V Foundation Board of Directors | ||
| 3:00pm | RISC-V ISA & Foundation Overview; Daily Prize Draw | Rick O’Connor, RISC-V Foundation | Slides |