Last Week in RISC-V: Friday November 9, 2018

By Palmer Dabbelt, Engineer at SiFive

OpenWRT Port

Zoltan has posted a patch set to add RISC-V support to OpenWRT, which is based on glibc right now. It supports SiFive’s VC707 dev kit, HiFive Unleashed, and QEMU. The port is experimental, but it’s a great way to get started with RISC-V embedded Linux development. The patch set is currently in a staging branch.

 

QOM Conversion of RISC-V Devices

Peter Maydell pointed out that a few of the RISC-V device models in QEMU haven’t been properly converted to QEMU’s Object Model. Conversion of these device models will aid us in building configurable QEMU machines. If you’re interested in getting started with RISC-V QEMU development, then this is a great place to start!

 

Stabilizing the RISC-V QEMU Port for the 3.1.0 Release

QEMU is in the release candidate phase of its release cycle, which means it’s time to start seriously testing the RISC-V QEMU port in order to try to shake out any bugs before release.

 

RISC-V FOSDEM Dev Room

RISC-V has been selected for a dev room at FOSDEM in 2019, where we’ll have a full day of RISC-V related talks and discussion. The deadline for abstract submission is November 25th, 2018. More details can be seen on the CFP.

 

Free open source RISC-V envelope model and free riscvOVPsim ISS from Imperas

Contributed by Simon from Imperas

Imperas has made available the source of their full RISC-V model – which covers the full 2.2+, 1.10+ specs and have also made available a free ISS that is configurable for all the options of the RISC-V specs. The free ISS: riscvOVPsim is available as part of the RISC-V compliance framework and with its configurability, debug and flexible tracing is used as one of the reference simulators by the compliance group. The model source is here, and the free riscvOVPsim can be downloaded here.

 

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