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Hex Five Adds MultiZone Security To The Andes RISC-V Cores On GOWIN FPGAs

By November 9, 2018May 12th, 2021No Comments

Hex Five Security, Inc, the creator of MultiZone™ Security, Andes Technology Corporation and GOWIN Semiconductor Corp announce a collaboration to enable MultiZoneTMSecurity, the first Trusted Execution Environment for RISC-V on the Andes N(X)25 RISC-V Cores, which is part of 25-series, with the GOWIN GW-2A Family of FPGAs.
Hex Five’s patent pending technology provides policy-based hardware-enforced separation for an unlimited number of security zones, with full control over data, code, interrupts and peripherals. MultiZone’s™ Configurator takes fully compiled and linked customer code and merges it with Hex Five’s nanoKernel to enable rapid adoption without any changes to hardware or customer code basis.
Andes 32-bit N25(F)/A25, and 64-bit NX25(F)/AX25 are versatile CPU cores compliant to RISC-V ISA that deliver over 3.5 CoreMark/MHz and 1.3 WMIPS/MHz for single precision floating point. Their common features include dynamic branch prediction, instruction and data caches, local memories, and Andes Custom Extension™ (ACE) to simplify instructions design for Domain-Specific Acceleration. All cores support User/Machine mode, while the A25/AX25 add Supervisor mode and MMU for Linux kernel and its applications.
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