Western Digital announced big plans for RISC-V with a new open source RISC-V core, an open standard initiative for cache coherent memory over a network, and an open source RISC-V instruction set simulator. The SweRV Core features a 2-way superscalar design with a 32-bit, 9 stage pipeline core. It has clock speeds of up to 1.8Ghz on a 28mm CMOS process technology and will be used in various internal embedded designs. The SweRV ISS offers full test bench support for RISC-V cores and was used to simulate and validate the SweRV Core. Finally, OmniXtend is an approach to providing cache coherent memory over an Ethernet fabric. Its memory-centric system architecture provides open standard interfaces for access and data sharing across processors, machine learning accelerators, GPUs, FPGAs and other components.
Codasip uncorked the latest version of its tool suite for development and verification of RISC-V processors. The tools allow designers to write a high-level description of a processor in the architecture description language CodAL and then automatically synthesize the design’s RTL, test bench, virtual platform models, and processor SDK. The methodology uses an Instruction Accurate processor model in CodAL for SDK generation and a Cycle Accurate model for implementation.
Microsemi announced a new architecture for SoC FPGAs that combines its low power mid-range PolarFire FPGA family and a microprocessor subsystem based on RISC-V. The architecture, developed with SiFive, provides real-time deterministic asymmetric multiprocessing (AMP) capability to Linux platforms in a multi-core coherent CPU cluster and features a flexible 2 MB L2 memory subsystem that can be configured as a cache, scratchpad or a direct access memory.
Andes Technology uncorked Andes Custom Extension (ACE) for its recently-announced line of RISC-V cores, allowing embedded designers to add customized instructions to Andes V5 CPU cores. The ACE design environment uses a description file that describes instruction input/output interfaces and instruction semantics in C and a concise Verilog file implementing the RTL logic based on the given interfaces to generate the extended CPU and software toolchains. It offloads all housekeeping RTL design tasks such as opcode selection, instruction decoding, operand mapping, input operand accesses, dependence checking and result gathering and requires no expertise in processor pipeline design.
Valtrix and Imperas teamed up to integrate Valtrix’s STING bare-metal software tool for verification of SoC implementations with Imperas’ free RISC-V instruction set simulator, riscvOVPsim. The integration allows for configuration of virtual platforms as a verification reference as well as extending the RISC-V envelope model with custom instructions. Additionally, Esperanto Technologies will use Valtrix’s STING for verification of its RISC-V-based 7nm AI SoC.
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