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Electronics Weekly Article: A View From The RISC-V Summit

By December 7, 2018May 12th, 2021No Comments

There were two announcements from IAR Systems in support of establishing a robust ecosystem for RISC-V. The first was with IP provider, SiFive, to collaborate on bringing the former’s compiler and debugger tools to the configurable processor core IP.
Integration of tools and IP is expected to support developers to deliver products and to increase deployment of the open, free instruction set architecture (ISA).
The software company also announced a partnership with CPU IP provider, Andes, to support the company’s RISC-V cores, the AndesCore N25(F)/NX25(F) and A25/AX25, in IAR Embedded Workbench  for RISC-V.  The first version will be available in mid-2019. AndeStar V5 instruction extension and Andes Custom Extension (ACE) instruction customisation capabilities will be coupled with Workbench to maximise code speed and minimise code size for RISC-V cores.
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