WHAT: RISC-V Workshop Taiwan Region is seeking speaking proposal and poster sessions for its upcoming RISC-V Workshop Taiwan region.
WHERE: Ambassador Hotel, No. 188號, Section 2, Zhonghua Rd, East District, Hsinchu City, Taiwan Region 30060
WHEN: Tuesday, March 12 to Wednesday, March 13, 2019
DETAILS: The RISC-V Foundation, in partnership with Informa’s Knowledge & Networking Division, KNect365, will hold the RISC-V Workshop Taiwan region. The call for speaking proposals and poster presentations for the Workshop in Taiwan region is now open until Friday, Jan. 11, 2019. Please submit your abstract here. The open, expansive and international RISC-V ecosystem in Asia will highlight current and prospective RISC-V projects and implementations, influencing the future evolution of the RISC-V instruction set architecture (ISA).
Submission Deadline: Friday, Jan. 11, 2019
Speaker Notification: Late-January
To register for the event, please visit: https://tmt.knect365.com/risc-v-workshop-taiwan/purchase/select-package.
To learn more about sponsorship opportunities, please visit: https://tmt.knect365.com/risc-v-workshop-taiwan/sponsor.
For press interested in attending, please email: firstname.lastname@example.org to receive your complimentary pass.
About RISC-V Foundation
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 200 member organizations building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.