Skip to main content
In the News

Sohu Article: On Wednesday, Top RISC-V Technology Big Cow Hu Zhenbo Talks About The Design And Development Of Open Source RISC-V Processor For Internet Of Things

By January 14, 2019May 12th, 2021No Comments

On Jan. 4, 2019, the Zhishang Open Class officially launched the RISC-V series, focusing on the Chinese RISC-V ecosystem. In this RISC-V series, SiFive China senior field application manager Hu Jin, director of SoC platform Wu Jun, Core Technology CEO Wang Zhenwen, and director of Marketing and Technology Services Wang Shengwen presented in three sessions. On January 9th, SiFive China senior field application manager Hu Jin and SoC platform director Wu Jun gave a lecture on the first lecture of RISC-V series called “RISC-V Ecological Status and Development Example”, which attracted Huawei HiSilicon. IC design engineers and electronic engineers from well-known semiconductor companies such as Ziguang Zhanrui, AMD, Intel and Anba Semiconductor as well as related teachers and students in microelectronics, integrated circuits, computer science and technology, such as Tsing Hua University, National Defense Science and Technology University, Chinese Academy of Sciences, and Harbin Institute of Technology. There are over 2,400 people listening to the live broadcast of the smart things open class.
To read more, please visit: Please note that the original article is in Chinese.

Stay Connected With RISC-V

We send occasional news about RISC-V technical progress, news, and events.