RISC-V EMEA Roadshow Spotlight: OneSpin Solutions

The RISC-V Foundation, in collaboration with the Linux Foundation, is hosting free, half-day “Getting Started with RISC-V” events in Tel Aviv, Munich, Berlin, Tallinn, Paris and London from Sept. 16-26. RISC-V Foundation members will give presentations and live demonstrations showcasing innovation RISC-V solutions and implementations. Register today to save your spot!

OneSpin Solutions is one of the featured RISC-V Foundation members in the EMEA roadshow, presenting the session, “Verifying the Full Scope of RISC-V Integrity.” OneSpin offers a range of EDA solutions for digital integrated circuits, which enables users to address design challenges in areas where reliability really counts: safety-critical verification, SystemC/C++ high-level synthesis (HLS) code analysis and FPGA equivalence checking. Read on to learn more about the company and what it will be showcasing at the events.

What applications or problems does your company’s technology solve for engineers?

  • OneSpin allows RISC-V processor core developers to fully verify their designs to assure integrity at all levels from functional correctness to safety, security and trust. This is essential as RISC-V developers must compete with more established processors in the market as well as other RISC-V processors. To stand out against the many available options, RISC-V processor core developers must thoroughly verify their designs. This requirement goes beyond Instruction Set Architecture (ISA) compliance checking to include optional ISA features, custom extensions and microarchitectural implementation choices. RISC-V system-on-chip (SoC) designers must be able to confirm the integrity of the RISC-V cores they integrate, including proof that no Trojans or hardware vulnerabilities lurk in the design, and verify that the cores are integrated properly into SoCs. Safety-critical applications with strict standards add even more verification requirements.

What does your company do regarding RISC-V? 

  • OneSpin provides a RISC-V verification solution that quickly and exhaustively verifies RISC-V processor designs and provides proof of compliance to the ISA with no gaps or inconsistencies.  The OneSpin RISC-V Integrity Verification Solution is the industry’s first commercial tool suite to address the needs of both core providers and core integrators. It leverages OneSpin’s advanced formal verification expertise for automotive and other high-integrity processor applications to exhaustively verify the implementation with minimal set up and runtime.
  • The core of the solution is the formalization of the RISC-V ISA as a set of SystemVerilog Assertions (SVA) using the unique OneSpin Operational Assertion approach. Operational SVA enables high-level, non-overlapping assertions that capture end-to-end transactions and requirements in a concise, elegant way. OneSpin’s RISC-V Integrity Verification Solution ensures that an IP core implementation does everything it’s supposed to do and does not do anything it’s not supposed to do.
  • Thanks to OneSpin, SoC designers can license a RISC-V core confident that it complies with the ISA specification, while IP vendors can support their own ecosystems and ensure that ecosystem partners also comply. Furthermore, SoC designers can add custom features to the RISC-V ISA to support their specific applications. OneSpin’s solution ensures nothing is broken as features are added and is flexible enough to verify new functionalities.To learn more, visit https://www.onespin.com/solutions/risc-v/.

 What will attendees learn from your presentation?

  • OneSpin’s talk presents a verification flow covering the full scope of integrity for RISC-V cores and SoCs, spanning functional correctness, safety, security, and trust. It is essential for RISC-V core developers, engineers evaluating cores for possible use, and SoC teams integrating RISC-V cores from internal or external sources.
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