FPGA Conference Europe

Structure of the intended talk:

• Short introduction of the speaker
• What is RISC-V?
  • Market environment of the RISC-V.
  • Licensing of the RISC-V ISA – in relation to ARM
  • Core Instruction Set and optional Extensions.
• How to implement a CPU in the classic way
  • Classic CPU design with separated datapath and controller.
• Implementing a CPU as a FSMD (FSM with an implicit datapath)
  • Outline of the FSMD concept.
• Comparison of the two concepts
  • Optimization possibilities in the datapath and the controller. Focusing on resource sharing of manual implementations and resulting area reductions.
  • Flexibility for future extensions and adaptions.
  • Strength of the FSMD concept in terms of code length.
  • Readability and easy understanding of a FSMD implementation. This is the main target of this implementation.
  • Easy and fast debugging due to little code length.
• Concept of my implementation
  • A complete CPU within two VHDL processes. One register process and one combinatorically process.
  • Complete register set as a record type.
  • Basic resources of this CPU implementation and actions during instruction processing.
• § Address progression
• § Status flags and their administration
• § Memory
• § Register set
  • Usage of special FPGA resources (Block RAM) and its integration into the FSMD concept.
• Explanation of the instruction set implementation in my design based on some instructions.
  • ADD: A very simple register-based instruction which is very common.
  • LOAD/STORE: Accessing external memory via the Avalon-Memory-Mapped-Bus.
  • JAL/JALR: Jump with link register. Frequently used for function calls.
  • A more complex instruction.
• Comparison of the synthesis results with common implementations
  • Further comparison of my design before and after optimizations with respect to chip area and maximum clock frequency.
• Verification methods used to verify my design.
• How to get access to my design.