HiPEAC Conference 2021

HiPEAC organizes four networking events per year: the HiPEAC Conference, two Computing Systems Weeks and a Summer School.

Collaboration and networking between member institutions and across the different disciplines: computer architects, design tool builders, compiler builders, system designers, between researchers from academia and industry, between European and non-European institutions. This collaboration between best of breed must lead to more European excellence in the HiPEAC domain. Collaboration and networking is stimulated by means of the various networking events, and the small collaboration incentives like collaboration grants, mini-sabbaticals, internships.

RISC-V Content

Tutorial: Jan 19, 1:30p, – 10:30 pm
Using gem5 and full- system RISC-V simulation to enable the optimization of heterogeneous architectures
Organizers: Marina Zapater, Associate Professor, University of Applied Sciences Western Switzerland (HES-SO) and Sergi Abadal, Distinguished Researcher, Universitat Politècnica de Catalunya (UPC)

This tutorial will provide an introduction to architectural simulation using the gem5-X simulation framework (which is an extended and improved version of the gem5 simulator) and demonstrate how the gXR5 extensions for gem5-X can be used to simulate a full-system Linux-capable RISC-V architecture.

Furthermore, we will showcase the benefits of full-system gem5 simulation for architectural exploration and optimization by showing how we can simulate three different architectural enhancements using gem5: (1) in-cache computing, (2) analog in-memory compute cores and (3) wireless interconnects; and we will describe how architectural evaluation (in terms of performance and power) can be performed.

This one-day tutorial will start by providing an overview on the capabilities of gem5-X and gXR5, followed by detailed descriptions of the three architectural enhancements proposed and the methodology followed. The afternoon session will include a hands-on technical session where we will get the audience acquainted with gem5-X and gXR5, showing them how to use these extensions to perform their simulations.

Workshop: Jan 20, 1:30pm – 5:00pm
De-RISC: Dependable Real-Time Safety-Critical RISC-V based Platforms
Several safety and mission-critical real-time systems, such as those in space and avionics domains, demand increased performance, reliable and easy to verify and validate platforms to match the requirements of highly autonomous missions and systems that need to undergo qualification and certification against safety guidelines and be commercialized worldwide minimizing export restrictions. Unfortunately, commercial platforms either fail to match domain-specific requirements for space and avionics (e.g. safety requirements), are limited by US export regulations, or simply fail both sets of requirements. This workshop introduces a number of talks around the development, from design to validation, and the use of hardware/software multicore platforms meeting those requirements. In particular, this workshop introduces concepts related to hardware Systems-on-Chip (SoCs), hypervisors, validation support, and use cases for RISC-V based systems supporting high integrity levels, mixed-criticality, high performance, and dependability, including those being developed as part of the H2020 De-RISC project, which targets TRL8 by 2022. In particular, this workshop targets the application of solutions amenable for high TRL systems, thus with a clear path towards deployment in real systems, thus facing challenges related to real implementations and commercial validation.