First International workshop on RISC-V for HPC

Co-located with ISC 2023, this is a half day workshop aims to continue building the community of RISC-V in HPC, sharing the benefits of this technology with domain scientists, tool developers, and supercomputer operators. There are numerous potential advantages that RISC-V can provide to HPC and, assuming the significant rate of growth of this technology to date continues, as we progress further into the decade it is highly likely that RISC-V will become more relevant and widespread for HPC workloads. Therefore it is important not only for the HPC community to gain more awareness about RISC-V, but given the open and collaborative nature of the architecture then HPC can help shape the future of RISC-V to ensure that it is suited for scientific and engineering workloads.

This workshop aims to bring together those already looking to popularise RISC-V in the field of HPC with the supercomputing community at-large. By sharing benefits of the architecture, success stories, and techniques we hope to further popularise the technology and increase involvement by the community.

There is currently a call for papers open until 24th March 2023 (AoE) see the workshop website for further details.