RISC-V for HPC workshop at SC24

Supercomputing is the world’s largest HPC conference, and the HPC SIG will be hosting a RISC-V for HPC workshop on the afternoon of Monday the 18th of November, 2pm to 5:30pm in Atlanta, USA as part of SC. The goal of this workshop is to continue building the community of RISC-V in HPC, sharing the benefits of this technology with domain scientists, tool developers, and supercomputer operators. Whilst RISC-V has become very popular already in some fields, and over thirteen billion RISC-V core have been shipped, to date it has yet to gain traction in HPC.

However, there are numerous potential advantages that RISC-V can provide to HPC and, assuming the significant rate of growth of this technology to date continues, as we progress further into the decade it is highly likely that RISC-V will become more relevant and widespread for HPC workloads. Furthermore, recent advances in RISC-V make it a more realistic proposition for HPC workloads than ever before, and an example of this is the new commodity available hardware that we are seeing be released and made generally available.

This workshop aims to bring together those already looking to popularise RISC-V in the field of HPC with the supercomputing community at-large. By sharing benefits of the architecture, success stories, and techniques we hope to further popularise the technology and increase involvement by the community.

We have a call for papers, with main paper deadline 9th August 2024 (AoE) and invite submissions of high-quality, original research results and works-in-progress on RISC-V with a general connection to HPC. For more details see the event website, which will be updated with the workshop schedule once this is determined.