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RISC-V Sessions at DAC 2016

By May 30, 2016October 1st, 2020No Comments

Be sure to join us at the 53rd Design Automation Conference in Austin Texas the week of June 6th, 2016 for some interesting RISC-V sessions.
Professor Krste Asanovic, UC Berkeley and Chairman of the RISC-V Foundation will deliver the Tuesday June 7th SKY Talk at 1pm in the DAC Pavilion entitled: “RISC-V: Instruction Sets Want To Be Free”.

The most important interface in a computer system is the instruction set architecture (ISA) as it connects software to hardware. So, given the prevalence of open standards for almost all other important interfaces, why is the ISA still proprietary? We argue that a free ISA is a necessary precursor to future hardware innovation, and there’s no good technical reason not to have free, open ISAs just as we have free, open networking standards and free, open operating systems. The free and open RISC-V ISA began development at UC Berkeley in 2010, with the frozen base user ISA standard released in May 2014, and has since seen rapid uptake around the globe, including the first commercial shipments. This talk will cover the technical features of the RISC-V ISA design , which has the goals of scaling from the tiniest implementations for IoT up to the largest warehouse-scale computers, with support for extensive customization. We’ll also describe three different industry-competitive open-source cores developed at UC Berkeley, all written in Chisel, a productive new open-source hardware design language. Finally, we’ll describe the uptake of RISC-V and the development of the RISC-V ecosystem, including the RISC-V Foundation.

Also, on Tuesday at 1:30pm as part of the Design IP Track we will present a 90min Designing with RISC-V tutorial in ballroom G covering:

DAC 2016 IP Track: Designing With RISC-V

This session consists of a brief 5min RISC-V Overview followed by three 25min tutorial presentations covering:

  • RISC-V Tool chain & OS environment – Andrew Waterman, SiFive;
  • RISC-V Security Enhancements using Bluespec – Andre DeHon, Draper Labs; and
  • RISC-V Rocket Core using Xilinx FPGAs – Alex Bradbury, lowRISC.

Rick O’Connor, Executive Director of the RISC-V Foundation, will present the RISC-V Overview and moderate the overall session.

RISC-V Tool chain & OS environment – Andrew Waterman, SiFive
Participants will learn about the design of the RISC-V architecture and platform including the standard compiler tool chain and operating system support. We will also cover the capabilities of the open-source Rocket Chip generator written in Chisel, including the various open-source processor core generators available within Rocket.

RISC-V Security Enhancements using Bluespec – Andre DeHon, Draper Labs
Participants will learn about a powerful processor extension and methodology that provides programmable security and safety interlocks, Software Defined Metadata Processing (SDMP), along with a methodology for developing and validating specialized RISC-V processors (Bluespec RISC-V Development Factory). Embedded processors running a low-level C and
assembly stack are important building blocks in today’s powerful SoCs. However, today’s embedded processor leave the burden of hardening the C software stack against malicious attacks (e.g. buffer overflows, control flow hijacking) to the developer. We show how a processor extension, SDMP, coupled with security policies can protect against these attacks.
Furthermore, we illustrate how Bluespec’s RISC-V Development Factory can validate customized RISC-V processors with the extensions to support SDMP. The RISC-V Development Factory provides GDB integration for embedded processor and software design and debug along with tandem verification to validate that the custom processor remains faithful to the RISC-V functional specification.

RISC-V SoCs on Xilinx FPGAs – Alex Bradbury, lowRISC
Participants will learn how to bring up the lowRISC SoC (derived from UC Berkeley’s Rocket
implementation) on Xilinx development boards and to customize it to their needs. We will pay particular attention to tagged memory and minion cores, both novel features which demonstrate our approach to creating a secure, flexible, and extensible SoC architecture. lowRISC is a not-for-profit project aiming to produce the ‘Linux of the hardware world’, providing an open-source System-on-Chip design for industry, academia, and the wider open source community to build upon.

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