RISC-V At Design Automation Conference (DAC)

Join the RISC-V Foundation at the 54th Design Automation Conference (DAC) conference at the Moscone Center West in San Francisco, California from June 25 – 27, 2018.

Visit Our Booth

The RISC-V Foundation booth will feature pods from member companies: Imperas, Microsemi, SiFive, Syntacore, UltraSoC and Western Digital. Visit us in West Hall, Level Two at Booth #2638.

Check Out Our Members’ Booths

Additional RISC-V member companies will be onsite at DAC:

• Andes Technology – West Hall, Level 2, Booth #2658
• Google – West Hall, Level 1, Booth #1251
• Huawei – West Hall, Level 2, Booth #2129
• IBM – West Hall, Level 1, Booth #1252
• Mentor – West Hall, Level 2, Booth #2621
• Mosis – West Hall, Level 2, Booth #1442
• NVIDIA – West Hall, Level 2, Booth #1437D
• QuickLogic – West Hall, Level 1, Booth #1338
• Samsung Electronics – West Hall, Level 2, Booth #2635

Take Part In Our Scavenger Hunt To Win Prizes

We’ll also host a fun scavenger hunt! You can find the scavenger hunt form at the RISC-V Foundation booth #2638. To participate, you will need to visit the pods of each of our additional participating member companies: Imperas, Syntacore, SiFive, Microsemi, UltraSoC and Western Digital.
At each pod, please speak with a company representative to receive a RISC-V sticker. Return your completed form to the RISC-V Foundation booth and share your business card to be entered to win one of the grand prizes.

Join Our Workshop

DAC has invited the Foundation to present the RISC-V Ecosystem – Reshaping The CPU Landscape workshop on June 24 from 1 p.m. to 4 p.m. PT in room 3018. The sessions will detail how the free and open RISC-V instruction set architecture (ISA) is creating a paradigm shift in industry, reinvigorating semiconductor design and reshaping traditional business models. Sessions will include:

• RISC-V ISA and Foundation Overview – Rick O’Connor, RISC-V Foundation
  • This session will present RISC-V, a free and open ISA. With broad industry adoption, RISC-V is finding its way into applications ranging from IoT to high end servers and supercomputing. This session provides an ISA introduction and a RISC-V Foundation overview.

• RISC-V – A Diversity of Core and Accelerator Choices – Markus Levy, NXP
  • This talk will present some of the notable aspects that make RISC-V attractive: formal support for different instruction subsets, range of OS support (bare metal to hypervisor) and extensibility for custom instructions. The session will review a few of the different RISC-V cores available and provide design considerations of a microcontroller-based core.

• RISC-V OS Landscape – Palmer Dabbelt, SiFive
  • This session will give an overview of the RISC-V operating systems landscape. The session will cover operating systems such as Zephyr and other RTOS offerings that target IoT/microcontroller applications. Attendees will also learn about embedded Linux distributions such as Yocto Linux as well as desktop/server operating systems such as Fedora, Debian, and FreeBSD.

• Designing a Custom RISC-V Core Using Chisel – Alex Badicioiu, NXP
  • In this session, we will show a hands on demo of the steps required to create custom instruction extensions for RISC-V using available open source tools.

Featured Keynotes and Panels

• Core Choices: How To Navigate The Brave New World Of IP (Panel)
  • When: Tuesday, June 26 at 3:00 p.m. – 3:45 p.m. PT (Booth 2161)
  • Key Panelist:  Rick O’Connor – RISC-V Foundation, Berkeley, CA
  • Other panelists: John Ronco – Arm, Ltd.,; Majid Bemanian – MIPS Technologies, Inc., Markus Levy – NXP Semiconductors
  • Moderator: Junko Yoshida at EE Times
  • Get the description and details here.

• A New Golden Age For Computer Architecture: Domain Specific Accelerators And Open RISC-V (Keynote)
  • When: Wednesday, June 27 at 9:20 a.m. – 10:00 a.m. PT (Room 3008)
  • Speaker: David A. Patterson, vice chair of the Foundation’s Board of Directors, Google Inc. & University of California, Berkeley
  • Get the description and details here.

• 58.3 PULP-HD: Accelerating Brain-Inspired High-Dimensional Computing on a Parallel Ultra-Low Power Platform (Panel)
  • When: Wednesday, June 27 at 3:30 p.m. – 4:30 p.m. PT (Room 3022)
  • Speaker: Fabio Montagna, University of Bologna
  • Key authors:  Abbas Rahimi, ETH Zurich and University of California, Berkeley; Davide Rossi, University of Bologna and ETH Zurich; Luca Benini, ETH Zurich and University of Bologna
  • Other authors: Fabio Montagna, University of Bologna; Simone Benatti, University of Bologna
  • Get the description and details here.

• Computing Minus Moore’s Law = ?!?! (Panel)
  • When: Wednesday, June 27 at 4:30 p.m. – 5:30 p.m. PT (Room 3024)
  • Key Panelist:  Krste Asanovic, University of California, Berkeley & SiFive Inc.
  • Other panelists: Kathy Wilcox, Advanced Micro Devices, Inc; David Brooks, Harvard University & Facebook; Yuan Xie, University of California, Santa Barbara
  • Moderator: Todd Austin, University of Michigan
  • Get the description and details here.

Full DAC RISC-V Talk Schedule

Please find the full RISC-V Talk Schedule for DAC 2018 below. The talks are will take place at the RISC-V Foundation Booth #2638.

Monday, June 25, 2018

Tuesday, June 26, 2018

Wednesday, June 27, 2018

Learn More

You can check out the full DAC program here. To schedule a meeting with RISC-V or a member organization, please email: RISC-V@racepointglobal.com.
To learn more about the free and open RISC-V ISA and the RISC-V Foundation, please visit: https://riscv.org/risc-v-foundation/. Stay up-to-date about the latest RISC-V news by following us on Twitter and LinkedIn.