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RISC-V Ecosystem Highlights Innovative RISC-V Projects at RISC-V Day Tokyo

By October 3, 2018October 1st, 2020No Comments

RISC-V members to present on RISC-V based products and solutions

WHERE: Keio University, Fujiwara Hall in the Kyosei Building at the Hiyoshi Campus, 4-1-1 Hiyoshi, Kohoku-Ku, Yokohama, Kanagawa, Japan, 223-8526
WHEN: Thursday, Oct. 18, 2018 from 8:00 to 19:00 JST
WHAT: The RISC-V Foundation will share updates on new projects and implementations from its international membership at RISC-V Day Tokyo, with a focus on current and prospective RISC-V projects and implementations. This event will highlight the growth of the RISC-V ecosystem across Asia. RISC-V Foundation member companies Andes Technology, Esperanto Technologies, Microchip Technology, SiFive, Syntacore and UltraSoC will present at RISC-V Day Tokyo.
Speaking sessions include:

  • Welcome
    • When: 9:15-9:30 JST
    • Who: Hideharu Amano, Keio University
  • A Perspective on the Role of Open-Source IP In National AI Chip Electronics Projects
    • When: 9:30-9:40 JST
    • Who: TBD
  • Introduction of Technologies and People Supporting RISC-V Ecosystem
    • When: 9:40-9:55 JST
    • Who: Msyksphinz, FPGA Diary Author
  • Fedora on RISC-V – Status and Plan
    • When: 9:55-10:10 JST
    • Who: Wei Fu, Red Hat
  • RISC-V Architecture Update
    • When: 10:10-10:30 JST
    • Who: Krste Asanovic, SiFive and UC Berkeley
  • Keynote: RISC-V, AI and Innovation
    • When: 10:30-11:00 JST
    • Who: Dave Ditzel, Esperanto Technologies
  • Security and Hypervisor: Hypervisor Extension
    • When: 11:30-11:45 JST
    • Who: Andrew Waterman, SiFive
  • RISC-V Open-Source Models and Virtual Platforms Coupled with Commercial Grade Simulation Technologies and Tools
    • When: 11:45-Noon JST
    • Who: Shuzo Tanaka, eSOL TRINITY Co., Ltd.
  • Making of the RISC-V Reader Japanese Translation
    • When: Noon-12:15 JST
    • Who: Andrew Waterman, SiFive, Eiji Yokota, Nikkei BP Consulting, Inc. and Hideya Kawahara, SH Consulting
  • Embracing a System Level Approach in the Real World: Combining Arm & RISC-V in Heterogeneous Designs
    • When: 12:15-12:30 JST
    • Who: Gajinder Panesar, UltraSoC
  • Implementing 64-bit RISC-V Chip with MMU, L1 and L2 Using Academic Shuttle in Japan
    • When: 12:30-12:45 JST
    • Who: Kesami Hagiwara, University of Electro-Communications
  • RISC-V Asia Pacific Regional Marketing Activities
    • When: 14:10-14:25 JST
    • Who: Alex Guo, Jinglue Semiconductor and Naomi Tsujioka, SH Consulting
  • Keynote: The Future of Broadcast and Broadband Services, and Expectation to Processors
    • When: 14:25-14:45 JST
    • Who: Masayaoshi Onishi, Japan Broadcasting Corporation Science & Technology Research Laboratories
  • Keynote: AI-nization of Rakuten, Inc.
    • When: 14:45-15:15 JST
    • Who: Masayuki Chatani, Rakuten Inc.
  • Esperanto ET-Maxion High Performance Out-of-Order RISC-V Processor
    • When: 15:45-16:00 JST
    • Who: Polychronis Xekalakis and Christopher Celio, Esperanto Technologies
  • TEE to Run Trusted OS on RISC-V and Related Technologies
    • When: 16:00-16:15 JST
    • Who: Kuniyasu Suzaki and Akira Tsukamoto, AIST: National Institute of Advanced Industrial Science and Technology
  • Extending RISC-V Solutions for AIoT
    • When: 16:15-16:30 JST
    • Who: Charlie Su, Andes Technology
  • Mi-V Embedded Ecosystem
    • When: 16:30-16:45 JST
    • Who: Krishnakumar Ranamoorthi, Microchip Technology
  • The SCR Family of RISC-V Compatible Processor IP
    • When: 16:45-17:00 JST
    • Who: Alexander Redkin, Syntacore
  • Opportunities and Challenges of Building Silicon in the Cloud
    • When: 17:25-17:45 JST
    • Who: Krste Asanovic, UC Berkeley and SiFive
  • CloudBEAR Processor IP Product Line
    • When: 17:45-18 JST
    • Who: Alexander Kozlov, CloudBEAR
  • FIPS140-2 Compliant Trust Module for RISC-V Core Complex
    • When: 18:00-18:15 JST
    • Who: Shumpei Kawasaki, SH Consulting
  • OpenWrt Porting for RISC-V
    • When: 18:15-18:30 JST
    • Who: Alex Guo, Jinglue Semiconductor
  • Performance and Cost Efficiency of Big-Endian on RISC-V
    • When: 18:30-18:45 JST
    • Who: Kuniyasu Suzaki and Akira Tsukamoto, AIST: National Institute of Advanced Industrial Science and Technology

For more information about RISC-V Day Tokyo, please visit: and to book your ticket, please visit:
To schedule a meeting with RISC-V or a member organization, please email: To learn more about the RISC-V Foundation, its open, free architecture and membership information, please visit:
About RISC-V Foundation
RISC-V (pronounced “risk-five”) is free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 100 member organizations building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.
Media Contacts:
Allison DeLeo
Racepoint Global for RISC-V Foundation
Phone: +1 (415) 694-6700

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