Ratification signifies another breakthrough for the thriving RISC-V ecosystem
San Francisco – March 9 2020 – The RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), today announced the ratification of the processor trace specification. The new standard trace encoder algorithm allows engineers and developers to see exactly what instructions a core is executing, step by step. The processor trace specification will be enormously helpful to aid debugging by exposing accurate and detailed traces of activity, with filtering capabilities to isolate the trace portions that matter.
“RISC-V is rapidly gaining popularity due to its open and modular design that supports customization on top of a standard core ISA,” said Krste Asanović, chairman of the RISC-V Foundation Board of Directors.
“The RISC-V ecosystem continues to showcase a large degree of interoperability among various vendors’ implementations. With the processor trace specification ratified, trace IP developers, SoC integration engineers, and debug software developers have agreed on a highly efficient compressed standard for representing program flow on a RISC-V core.”
Designing and developing software can take months, and in some cases, longer depending on the size and complexity of the workload. General-purpose and legacy ISAs are not designed to accommodate the growing computing demands, pushing the industry to leverage RISC-V and its open collaboration model. Developers and engineers welcoming RISC-V and its open standard collaboration approach will now be able to capitalize on the processor trace specification and minimize time spent debugging and integrating tools and standard extensions.
“Understanding a system’s program behavior is often quite difficult, especially when working with complex systems for the HPC, Internet of Things, machine learning and artificial intelligence,” said Gajinder Panesar, chairman of the RISC-V Foundation’s Trace and Debug Standing Committee.
“Developers and engineers spend around 50-75 percent of their time debugging and integrating tools and extensions. With the processor trace specification ratified, users are able to choose core vendors and trace encoder suppliers knowing tools vendors will support this standard moving forward.”
RISC-V member companies Andes Tech, Blue Spec, Codasip, Esperanto, ETH Zurich, Seagate, SiFive, Syntacore, UltraSoC, Ventana Micro Systems, Western Digital, and others contributed to the ratification of the processor trace specification. The RISC-V Foundation’s Processor Trace Task Group is in the process of enhancing the trace ecosystem and will propose plans to the newly formed Trace and Debug Steering committee for its consideration and guidance.
The RISC-V Foundation has seen significant growth over the past few years with more than 531 organizations, individuals and universities from 32 countries and six continents around the world. The RISC-V ISA continues to witness rising commercial adoption and implementations across a variety of industries.
To check out the RISC-V processor trace specification, please visit: https://riscv.org/specifications/
About RISC-V Foundation
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 531 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.
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